mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 31

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 6:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
Current
State
Any
Idle
Row active
Read (auto-
precharge
Disabled
Write (auto-
precharge
disabled)
Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6; notes appear below and on next page
CS#
Notes:
H
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after
2. This table is bank-specific, except where noted (the current state is for a specific bank and
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. Issue
RAS#
H
H
H
H
H
H
H
(if the previous state was self refresh).
the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge
occurring during these states. Allowable commands to the other bank are determined by its
current state and this table, and according to Table 7 on page 33.
X
L
L
L
L
L
L
Idle:
Row
active:
Read:
Write:
Precharging:
Read with auto
precharge enabled:
Row activating:
Write with auto
precharge enabled:
CAS#
H
H
H
H
H
X
L
L
L
L
L
L
L
L
The bank has been precharged,
complete.
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated.
WE#
H
H
H
H
H
H
X
L
L
L
L
L
L
L
Starts with registration of a PRECHARGE command and ends when
t
Starts with registration of a READ command with auto precharge
enabled and ends when
bank will be in the idle state.
Starts with registration of an ACTIVE command and ends when
t
state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
bank will be in the idle state.
RP is met. Once
RCD is met. Once
31
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous
operation)
ACTIVE (select and activate row)
REFRESH
LOAD MODE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (start PRECHARGE)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (start PRECHARGE)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RP is met, the bank will be in the idle state.
t
RCD is met, the bank will be in the “row active”
Command/Action
2Gb: x4, x8, x16 DDR2 SDRAM
t
t
t
RP has been met, and any READ burst is
RP has been met. Once
RP has been met. Once
t
Command Truth Tables
RCD has been met. No data
©2006 Micron Technology, Inc. All rights reserved.
t
XSNR has been met
t
t
RP is met, the
RP is met, the
Notes
9, 10
7
7
9
9
8
9
8
9
9
8