mt47h128m16hg-3-it Micron Semiconductor Products, mt47h128m16hg-3-it Datasheet - Page 94

• Manufacturer Part Number: mt47h128m16hg-3-it
• Description: 2gb X4, X8, X16 Ddr2 Sdram
• Manufacturer: Micron Semiconductor Products

Table 29:
PDF: 09005aef824f87b6/Source: 09005aef824f1182
2gb_ddr2.fm - Rev. A 9/06 EN
(V/ns)
Slew
Rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
Δ
125
83
4.0 V/ns
S
t
0
–
–
–
–
–
–
D
DDR2-400/533
Notes: 1–7; all units in ps
Δ
45
21
H
0
t
–
–
–
–
–
–
D
Notes:
Δ
125
–11
3.0 V/ns
83
S
0
t
–
–
–
–
–
D
1. For all input signals, the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be obtained
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 31 are the DQS single-
Δ
–14
45
21
H
t
0
–
–
–
–
–
D
value to the derating value listed in Table 29.
t
of V
defined as the slew rate between the last crossing of V
V
shaded “V
the actual signal is later than the nominal slew rate line anywhere between shaded
“V
level to DC level is used for derating value (see Figure 74).
t
ing of V
nal is defined as the slew rate between the last crossing of V
of V
shaded “DC level to V
Figure 75). If the actual signal is earlier than the nominal slew rate line anywhere between
shaded “DC to V
DC level to V
will not have reached V
signal is still required to complete the transition and reach V
by linear interpolation.
characterization.
ended slew rate derating with DQS referenced at V
t
t
and
(
t
DS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
DH nominal slew rate for a rising signal is defined as the slew rate between the last cross-
DS
DH
t
DS,
IL
DS
REF
(
b
AC
a
Δ
125
a
–11
–25
REF
REF
t
2.0 V/ns
83
) for DDR2-667. Table 33 provides the V
and
S
DH
t
0
–
–
–
–
(
and
t
) MAX. If the actual signal is always earlier than the nominal slew rate line between
D
DC
DH Derating Values with Differential Strobe
(
DC
(DC). If the actual signal is always later than the nominal slew rate line between
IL
a
) to AC region,” the slew rate of a tangent line to the actual signal from the AC
) for DDR2-533. Table 34 provides the V
(
t
) and the first crossing of V
DC
DH
t
Δ
REF
–14
–31
DH
45
21
H
t
0
–
–
–
–
D
) MAX and the first crossing of V
REF
(
b
a
DC
. Table 32 provides the V
) for DDR2-400.
(
DQS, DQS# Differential Slew Rate
) to AC region,” use nominal slew rate for derating value (see Figure 73). If
REF
DC
Δ
–13
–31
95
12
1.8 V/ns
S
1
t
–
–
–
–
D
) level is used for derating value (see Figure 76).
(
DC
REF
) region,” the slew rate of a tangent line to the actual signal from the
Δ
–19
–42
IH
33
12
–2
H
t
–
–
–
–
(
D
DC
(
AC
) region,” use nominal slew rate for derating value (see
)/V
94
Δ
–19
–43
t
1.6 V/ns
24
13
–1
t
S
–
–
–
–
DS and
IL
D
(
AC
) at the time of the rising clock transition), a valid input
Δ
–30
–59
24
10
–7
H
IH
t
–
–
–
–
D
t
(
REF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DH required is calculated by adding the data sheet
AC
) MIN.
-based fully derated values for the DQ (
Δ
–31
–74
25
11
1.4 V/ns
–7
S
t
–
–
–
–
D
REF
REF
-based fully derated values for the DQ (
2Gb: x4, x8, x16 DDR2 SDRAM
(
t
Δ
DC
REF
–18
–47
–89
DS nominal slew rate for a falling signal is
22
H
5
t
–
–
–
–
D
).
REF
-based fully derated values for the DQ
t
DH nominal slew rate for a falling sig-
and DQ referenced at the logic levels
–127 –140 –115 –128 –103 –116
Δ
REF
–19
–62
1.2 V/ns
23
Input Slew Rate Derating
t
S
5
–
–
–
–
D
(
DC
IH
) and the first crossing of
IH
Δ
–35
–77
(
17
–6
DC
H
(
t
–
–
–
–
AC
D
©2006 Micron Technology, Inc. All rights reserved.
) MIN and the first crossing
)/V
Δ
–50
IL
17
1.0 V/ns
–7
S
t
–
–
–
–
–
(
D
AC
).
Δ
–23
–65
H
6
t
–
–
–
–
–
D
Δ
–38
0.8 V/ns
t
S
5
t
–
–
–
–
–
–
DS
D
a
and
t
Δ
–11
–53
DS
H
t
–
–
–
–
–
–
D
a