gwixp425bdt Intel Corporation, gwixp425bdt Datasheet

no-image

gwixp425bdt

Manufacturer Part Number
gwixp425bdt
Description
Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
Manufacturer
Intel Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GWIXP425BDT
Manufacturer:
INTEL
Quantity:
48
Company:
Part Number:
GWIXP425BDT
Quantity:
10
Intel
Processors and IXC1100 Control Plane
Processor
Product Features
For a complete list of product features, see
Typical Applications
I
I
I
I
I
The following features do not require
enabling software:
I
I
I
I
I
I
I
I
I
I
I
High-Performance DSL Modem
High-Performance Cable Modem
Residential Gateway
SME Router
Network Printers
Intel XScale
PCI Interface
USB v1.1 Device Controller
SDRAM Interface
High-Speed UART
Console UART
Internal Bus Performance Monitoring Unit
16 GPIOs
Four Internal Timers
Packaging
Commercial/Extended Temperature
— 492-pin PBGA
®
IXP42X Product Line of Network
®
Core — Up to 533 MHz
“Product Features” on page
The following features do require
enabling software:
I
I
I
I
I
I
Note:
I
I
I
I
I
Encryption/Authentication
(AES,DES,3DES,SHA-1,MD5)
Two High-Speed, Serial Interfaces
Three Network Processor Engines
Up to two MII Interfaces
One UTOPIA-2 Interface
Multi-Channel HDLC
Control Plane
Integrated Access Device (IAD)
Set-Top Box
Access Points (802.11a/b/g)
Industrial Controllers
Document Number: 252479, Revision: 005
Refer to the Intel
Programmer’s Guide for information on
which features are currently enabled.
11.
®
IXP400 Software
Datasheet
March 2005

Related parts for gwixp425bdt

gwixp425bdt Summary of contents

Page 1

... Network Printers I Datasheet “Product Features” on page 11. The following features do require enabling software: Encryption/Authentication I (AES,DES,3DES,SHA-1,MD5) Two High-Speed, Serial Interfaces I Three Network Processor Engines two MII Interfaces I One UTOPIA-2 Interface I Multi-Channel HDLC I ® Note: Refer to the Intel IXP400 Software Programmer’s Guide for information on which features are currently enabled ...

Page 2

... Paragon, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, Sound Mark, The Computer Inside, The Journey Inside, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...

Page 3

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Contents 1.0 Introduction.................................................................................................................................... 9 1.1 About this Document ............................................................................................................ 9 1.2 Product Features ................................................................................................................ 11 1.2.1 Product Line Features ........................................................................................... 11 1.2.2 Processor Features ............................................................................................... 14 2.0 Functional Overview ................................................................................................................... 15 2.1 Functional Units .................................................................................................................. 20 2.1.1 Network Processor Engines (NPEs) ...................................................................... 20 2.1.2 Internal Bus............................................................................................................ 21 2.1.2.1 North AHB ..............................................................................................21 2.1.2.2 South AHB ............................................................................................. 22 2.1.2.3 APB Bus................................................................................................. 22 2.1.3 MII Interfaces ......................................................................................................... 22 2 ...

Page 4

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Pro- cessor 4.3.2 Extended Temperature .......................................................................................... 81 5.0 Electrical Specifications ............................................................................................................. 82 5.1 Absolute Maximum Ratings ................................................................................................ 82 5 CCPLL1 CCPLL2 5.2.1 V Requirement ............................................................................................ 82 CCPLL1 5.2.2 V Requirement ............................................................................................ 83 CCPLL2 5.2.3 V Requirement .......................................................................................... 83 CCOSCP 5.2.4 V Requirement ............................................................................................ 84 CCOSC 5.3 RCOMP Pin Requirements................................................................................................. 85 5.4 DC Specifications ............................................................................................................... 85 5.4.1 Operating Conditions ............................................................................................. 85 5.4.2 PCI DC Parameters ............................................................................................... 86 5 ...

Page 5

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figures ® 1 Intel IXP425 Network Processor Block Diagram ...................................................................... 15 ® 2 Intel IXP423 Network Processor Block Diagram ...................................................................... 16 ® 3 Intel IXP422 Network Processor Block Diagram ...................................................................... 17 ® 4 Intel IXP421 Network Processor Block Diagram ...................................................................... 18 ® ...

Page 6

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Pro- cessor Tables 1 Related Documents ...................................................................................................................... 9 2 Terminology and Acronyms .......................................................................................................... 9 3 Processor Features .................................................................................................................... 14 4 Processor Functions................................................................................................................... 20 5 Signal Type Definitions............................................................................................................... 33 6 SDRAM Interface........................................................................................................................ 34 7 PCI Controller ............................................................................................................................. 36 8 High-Speed, Serial Interface 0 ................................................................................................... 38 9 High-Speed, Serial Interface 1 ...

Page 7

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 48 MII Output Timings Values ......................................................................................................... 98 49 MII Input Timings Values ............................................................................................................ 98 50 MDIO Timings Values................................................................................................................. 99 51 SDRAM Input Timings Values ..................................................................................................100 52 SDRAM Output Timings Values ...............................................................................................100 53 Signal Timing With Respect to Clock Rising Edge ...................................................................101 ® ...

Page 8

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Pro- cessor Revision History Date Revision March 2005 005 June 2004 004 April 2004 003 May 2003 002 February 2003 001 March 2005 8 Document Number: 252479, Revision: 005 Description 1. Rearranged product features lists in Features” ...

Page 9

... IXP400 Software Specification Update ® Intel XScale Core Developer’s Manual ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines ® Intel XScale Microarchitecture Technical Summary PCI Local Bus Specification, Rev. 2.2 Universal Serial Bus Specification, Revision 1.1 PC133 SDRAM Specification Table 2 ...

Page 10

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 2. Terminology and Acronyms (Continued) Acronym/ Terminology DDR Double Data Rate DES Data-Encryption Standard DMA Direct Memory Access DSP Digital Signal Processor E1 Euro 1 trunk line FIFO First In First Out ...

Page 11

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 1.2 Product Features 1.2.1 Product Line Features Table 3 on page 14 Processors and IXC1100 Control Plane Processor. ® • Intel XScale Core (compliant with ARM — High-performance processor based on Intel XScale — Seven/eight-stage Intel — ...

Page 12

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor — 16 endpoints • SDRAM interface — 32-bit data — 13-bit address — 133 MHz — eight open pages simultaneously maintained — Programmable auto-refresh — Programmable CAS/data delay — Support for 8 MB, minimum 256 MB maximum • ...

Page 13

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Used to offload typical Layer-2 networking functions such as: — Ethernet filtering — ATM SARing — HDLC • Encryption/Authentication — DES — DES 3 — AES 128-bit and 256-bit • Two MII interfaces — ...

Page 14

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 1.2.2 Processor Features Table 3. Processor Features ® Requires Intel IXP425 Enabling Network Feature Software Processor (Note 1) B0 Step Processor Speed 266/400/533 (MHz) UTOPIA 2 Yes X GPIO X UART 0/1 X HSS 0 Yes X HSS 1 Yes ...

Page 15

... Functional Overview ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor are compliant with the ARM product line and IXC1100 control plane processors are designed with Intel 0.18-µ production semiconductor process technology. This process technology — along with the compactness of the Intel XScale core, the ability to simultaneously process up to three integrated network processing engines (NPEs), and numerous dedicated-function peripheral interfaces — ...

Page 16

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 2. Intel IXP423 Network Processor Block Diagram March 2005 16 Document Number: 252479, Revision: 005 Datasheet ...

Page 17

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 3. Intel IXP422 Network Processor Block Diagram MII-0 MII-1 66.66 MHz Advanced Peripheral us Datasheet Document Number: 252479, Revision: 005 133.32 MHz x 32 bits North Advance High-Performance us Queue Status us 133.32 MHz x 32 bits South Advance High-Performance us ...

Page 18

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 4. Intel IXP421 Network Processor Block Diagram MII-0 66.66 MHz Advanced Peripheral us March 2005 18 Document Number: 252479, Revision: 005 HSS-0 UTOPIA 2 133.32 MHz x 32 bits North Advance High-Performance us Queue Status us 133 ...

Page 19

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 5. Intel IXP420 Network Processor Block Diagram MII-0 MII-1 66.66 MHz Advanced Peripheral us Datasheet Document Number: 252479, Revision: 005 133.32 MHz x 32 bits North Advance High-Performance us Queue Status us 133.32 MHz x 32 bits South Advance High-Performance us ...

Page 20

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 2.1 Functional Units The following sections briefly describe the functional units and their interaction in the system. For more detailed information, refer to the Intel IXC1100 Control Plane Processor Developer’s Manual. ...

Page 21

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor In addition to having separate instruction/data memory and local-code store, the NPE core supports hardware multi-threading with support for multiple contexts. The support of hardware multi- threading creates an efficient processor engine with minimal processor stalls due to the ability of the processor core to switch contexts in a single clock cycle, based on a prioritized/preemptive basis ...

Page 22

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Once the AHB/AHB bridge has obtained the read information from the peripheral on the South AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has the data for the master that requested the “ ...

Page 23

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 2.1.4 UTOPIA 2 The integrated, UTOPIA-2 interface works with a network processing engine, for several of the IXP42X product line and IXC1100 control plane processors. (See The UTOPIA-2 interface supports a single multiple-physical-interface configuration with cell-level or octet-level handshaking ...

Page 24

... IXP42X product line and IXC1100 control plane processors. The high-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. For a list of supported protocols, see the Intel Programmer’s Guide. March 2005 ...

Page 25

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 2.1.10 High-Speed and Console UARTs The UART interfaces are 16550-compliant UARTs with the exception of transmit and receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 UART specification. ...

Page 26

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 2.1.14 Timers The IXP42X product line and IXC1100 control plane processors consists of four internal timers operating at 66.66 MHz (which OSC_IN input pin.) to allow task scheduling and prevent software lock-ups. The device has four 32-bit counters: • ...

Page 27

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor • Eight-entry write buffer allows the core to continue execution while data is written to memory • Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with 40-bit accumulation for efficient, high-quality media and signal processing • ...

Page 28

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor The memory pipe has eight stages: • The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute then finish with the following memory stages: • Data Cache 1 • ...

Page 29

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 2.2.3 Instruction Memory Management Unit (IMMU) For instruction pre-fetches, the IMMU controls logical-to-physical address translation, memory access permissions, memory-domain identifications, and attributes (governing operation of the instruction cache). The IMMU contains a 32-entry, fully associative instruction-translation, look- aside buffer (ITLB) that has a round-robin replacement policy ...

Page 30

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor The I-cache can be enabled or disabled. Attribute bits within the descriptors — contained in the ITLB of the IMMU — provide some control over an enabled I-cache. When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical word first) from memory via a two-level, deep-fetch queue ...

Page 31

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Fill Buffer (FB) and Pend Buffer (PB) 2.2.8 The four-entry fill buffer (FB) works with the core to hold non-cacheable loads until the bus controller can act on them. The FB and the four-entry pend buffer (PB) work with the D-cache and mini-data cache to provide “ ...

Page 32

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 2.2.11 Performance Monitoring Unit (PMU) The performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter. The event counters can be programmed to monitor I-cache hit rate, data caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count ...

Page 33

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 3.0 Functional Signal Descriptions Listed in the signal definition tables — starting at pull-up an pull-down resistor recommendations that are required when the particular enabled interface is not being used in the application. These external resistor requirements are only needed if the particular model of Intel the particular interface enabled and the interface is not required in the application ...

Page 34

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor • Table 8 — High-Speed, Serial Interface 0 • Table 9 — High-Speed, Serial Interface 1 • Table 10 — MII Interfaces • Table 11 — UTOPIA-2 Interface • Table 12 — Expansion Bus Interface • ...

Page 35

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 6. SDRAM Interface (Sheet Name SDM_CKE SDM_DQM[3:0] 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. ...

Page 36

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 7. PCI Controller (Sheet Power Name Reset PCI_AD[31:0] PCI_CBE_N[3:0] PCI_PAR PCI_FRAME_N PCI_TRDY_N PCI_IRDY_N PCI_STOP_N PCI_PERR_N PCI_SERR_N 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 37

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 7. PCI Controller (Sheet Power Name Reset PCI_DEVSEL_N PCI_IDSEL PCI_REQ_N[3:1] PCI_REQ_N[0] PCI_GNT_N[3:1] PCI_GNT_N[0] PCI_INTA_N PCI_CLKIN 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 38

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 8. High-Speed, Serial Interface 0 Name HSS_TXFRAME0 HSS_TXDATA0 HSS_TXCLK0 HSS_RXFRAME0 HSS_RXDATA0 HSS_RXCLK0 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 39

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 9. High-Speed, Serial Interface 1 Name HSS_TXFRAME1 HSS_TXDATA1 HSS_TXCLK1 HSS_RXFRAME1 HSS_RXDATA1 HSS_RXCLK1 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 40

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 10. MII Interfaces (Sheet Name ETH_TXCLK0 ETH_TXDATA0[3:0] ETH_TXEN0 ETH_RXCLK0 ETH_RXDATA0[3:0] ETH_RXDV0 ETH_COL0 ETH_CRS0 ETH_MDIO 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 41

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 10. MII Interfaces (Sheet Name ETH_MDC ETH_TXCLK1 ETH_TXDATA1[3:0] ETH_TXEN1 ETH_RXCLK1 ETH_RXDATA1[3:0] ETH_RXDV1 ETH_COL1 ETH_CRS1 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 42

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 11. UTOPIA-2 Interface (Sheet Name UTP_OP_CLK UTP_OP_FCO UTP_OP_SOC UTP_OP_DATA[7:0] UTP_OP_ADDR[4:0] UTP_OP_FCI UTP_IP_CLK 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 43

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 11. UTOPIA-2 Interface (Sheet Name UTP_IP_FCI UTP_IP_SOC UTP_IP_DATA[7:0] UTP_IP_ADDR[4:0] UTP_IP_FCO 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 44

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 12. Expansion Bus Interface Power Name Reset EX_CLK EX_ALE EX_ADDR[23:0] EX_WR_N EX_RD_N EX_CS_N[7:0] EX_DATA[15:0] EX_IOWAIT_N EX_RDY[3:0] 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 45

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 13. UART Interfaces Power Name On 1 Reset RXDATA0 Z TXDATA0 Z CTS0_N H RTS0_N H RXDATA1 Z TXDATA1 Z CTS1_N H RTS1_N H 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 46

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 14. USB Interface Power Name Reset USB_DPOS USB_DNEG 1. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. ...

Page 47

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 16. GPIO Interface (Sheet Power Name On 1 Reset GPIO[13] Z GPIO[14] Z GPIO[15 While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. 2. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. † ...

Page 48

... IMPORTANT NOTE: When a system-level reset is asserted to the Intel Network Processors and IXC1100 Control Plane Processor — either via a power-on reset, a system reset Watchdog-Timer reset — and any interface active transaction (particularly the PCI bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a reset of other attached devices may be required ...

Page 49

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 19. Power Interface (Sheet Name Type VCCOSC I VSSOSC I VCCPLL1 I VCCPLL2 I † For a legend of the Type codes, see Datasheet Document Number: 252479, Revision: 005 † Description 1.3-V power supply input pins used for the internal logic of the analog oscillator circuitry ...

Page 50

... Package and Pinout Information ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have a 492-ball, plastic ball grid array (PBGA) package for commercial-temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (H) for extended-temperature applications ...

Page 51

... Document Number: 252479, Revision: 005 i FWIXP42 XBX <FPO> INTEL M C 2002 <ATPO> YWW KOREA Speed Stepping Part # (MHz) B-0 533 FWIXP425BD B-0 400 FWIXP425BC B-0 266 FWIXP425BB 533 B-0 Extended GWIXP425BDT Temperature 400 B-0 Extended GWIXP425BCT Temperature 266 B-0 Extended GWIXP425BBT Temperature B-0 266 FWIXP423BB B-0 266 FWIXP422BB B-0 266 FWIXP421BB * Level 1 Name ...

Page 52

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 20. Part Numbers (Sheet Device ® Intel IXP420 Network Processor ® Intel IXP420 Network Processor ® Intel IXP420 Network Processor ® Intel IXP420 Network Processor ® Intel IXC1100 ...

Page 53

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 4.2 Signal-Pin Descriptions In this section, separate ball-map-assignment tables are given for each model of the IXP42X product line and IXC1100 control plane processors. These tables include: Device ® Intel IXP425 Network Processor ® ...

Page 54

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 21. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 ...

Page 55

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 21. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

Page 56

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 21. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 ...

Page 57

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 21. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 HSS_TXDATA0 U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

Page 58

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 21. Ball Map Assignment for the Intel Ball Signal AA1 HSS_RXDATA0 AA2 VCCP AA3 VSS AA4 HSS_RXCLK1 AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] AA10 VCC ...

Page 59

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 21. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP AE10 VCCPLL1 ...

Page 60

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 SDM_DATA[8] A15 ...

Page 61

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 ...

Page 62

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

Page 63

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 ...

Page 64

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 N/C U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

Page 65

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal AA1 N/C AA2 VCCP AA3 VSS AA4 N/C AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 ETH_TXDATA1[1] AA10 VCC AA17 VCC ...

Page 66

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 22. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ETH_RXDV1 AE7 VSS AE8 ETH_COL1 AE9 VCCP AE10 VCCPLL1 ...

Page 67

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] A11 SDM_DATA[11] A12 SDM_DATA[10] A13 SDM_DATA[6] A14 SDM_DATA[8] A15 ...

Page 68

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 ...

Page 69

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 VCC J24 EX_ADDR[23] J25 EX_CS_N[2] J26 EX_CS_N[4] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

Page 70

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS N14 VSS N15 VSS N16 VSS N22 VCC N23 ...

Page 71

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 HSS_TXDATA0 U6 VCC U21 VCC U22 GPIO[14] U23 EX_RDY_N[1] U24 EX_RDY_N[2] U25 GPIO[15] U26 EX_DATA[15] Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

Page 72

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal AA1 HSS_RXDATA0 AA2 VCCP AA3 VSS AA4 HSS_RXCLK1 AA5 ETH_TXDATA0[2] AA6 VCC AA7 ETH_RXDATA0[1] AA8 VSS AA9 N/C AA10 VCC AA17 ...

Page 73

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 23. Ball Map Assignment for the Intel Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 N/C AE5 VCCP AE6 N/C AE7 VSS AE8 N/C AE9 VCCP AE10 VCCPLL1 AE11 VSS AE12 ...

Page 74

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal A1 PCI_AD[27] A2 PCI_GNT_N[1] A3 PCI_GNT_N[3] A4 SDM_DATA[19] A5 SDM_DATA[27] A6 SDM_DATA[26] A7 SDM_DATA[25] A8 SDM_DATA[23] A9 SDM_DATA[14] A10 SDM_DATA[13] ...

Page 75

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal E1 PCI_AD[23] E2 VCCP E3 PCI_REQ_N[2] E4 VSS E5 PCI_GNT_N[0] E6 SDM_DATA[16] E7 VCCP E8 SDM_DATA[30] E9 VSS E10 SDM_DATA[22] ...

Page 76

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal J1 PCI_CLKIN J2 VCCP J3 VSS J4 PCI_AD[22] J5 VSS J6 PCI_AD[29] J21 EX_ADDR[8] J22 EX_ADDR[16] J23 ...

Page 77

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal N1 PCI_AD[11] N2 VCCP N3 VCC N4 PCI_PERR_N N5 PCI_AD[15] N11 VSS N12 VSS N13 VSS ...

Page 78

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal U1 PCI_AD[8] U2 VCCP U3 PCI_AD[0] U4 PCI_AD[7] U5 N/C U6 VCC U21 VCC U22 GPIO[14] U23 ...

Page 79

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal AA1 N/C AA2 VCCP AA3 VSS AA4 N/C AA5 ETH_TXDATA0[2] AA6 VCC AA7 ...

Page 80

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 24. Ball Map Assignment for the Intel ® and Intel IXC1100 Control Plane Processor (Sheet Ball Signal AE1 ETH_RXDATA0[3] AE2 VCCP AE3 ETH_COL0 AE4 ETH_TXEN1 AE5 VCCP AE6 ...

Page 81

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 4.3 Package Thermal Specifications The thermal characterization parameter “< between the top, center of the package and the junction temperature. This can be a useful value for verifying device temperatures in an actual environment. By measuring the package of the device, the junction temperature can be estimated, if the thermal characterization parameter has been measured under similar conditions ...

Page 82

... CCPLL1 CCPLL2 To reduce voltage-supply noise on the analog sections of the Intel Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits ( and oscillator circuit (V CCPLL2 The filter circuits for each supply are shown in the following sections. 5.2.1 V ...

Page 83

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 9. V Power Filtering Diagram CCPLL1 1 5.2.2 V Requirement CCPLL2 A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — for a first- order filter with a cut-off frequency below 30 MHz — must be connected to the V IXP42X product line and IXC1100 control plane processors ...

Page 84

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor When 170 inconvenient size, capacitor values between 150 nF to 200 nF could be used with little adverse effects, assuming that the effective series resistance of the 200-nF capacitor is under 50 m:. In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other ...

Page 85

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.3 RCOMP Pin Requirements Figure 13 shows the requirements for the RCOMP pin. Figure 13. RCOMP Pin External Resistor Requirements 5.4 DC Specifications Operating Conditions 5.4.1 Table 25. Operating Conditions Symbol V Voltage supplied to the I/O. CCP V Voltage supplied to the internal logic. ...

Page 86

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor PCI DC Parameters 5.4.2 Table 26. PCI DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN I/O or output pin C OUT capacitance ...

Page 87

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.4.4 UTOPIA-2 DC Parameters Table 28. UTOPIA-2 DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL Output current at high I OH voltage Output current at low I OL voltage I Input-leakage current ...

Page 88

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.4.6 MDIO DC Parameters Table 30. MDIO DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN C Input-pin capacitance INMDIO Note: 1 ...

Page 89

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 32. Expansion Bus DC Parameters (Sheet Symbol Parameter V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN Notes: 1. Test conditions were load to ground. 2. These values are typical values seen by the manufacturing process and are not tested. ...

Page 90

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor High-Speed and Console UART DC Parameters 5.4.11 Table 35. UART DC Parameters Symbol Parameter V Input-high voltage IH V Input-low voltage IL V Output-high voltage OH V Output-low voltage OL I Input-leakage current IL C Input-pin capacitance IN Note: 1. These values are typical values seen by the manufacturing process and are not tested. ...

Page 91

... Please refer to the Intel IXC1100 Control Plane Processor Product Line: Crystal Design Considerations Application Note (Document Number 305588), and contact Intel for the recommended Intel of Network Processors and IXC1100 Control Plane Processor part number optimized for use with crystal oscillators. Device Clock Timings Table 39 ...

Page 92

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Device Clock Timings Table 39. Symbol C Load capacitance 1 C Load capacitance 2 T Duty cycle DC Notes: 1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. ...

Page 93

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 14. Typical Connection to a Crystal Figure 15. Typical Connection to an Oscillator Datasheet Document Number: 252479, Revision: 005 ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane Processor OSC_IN C 1 XTAL ...

Page 94

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.1.2 PCI Clock Timings Table 41. PCI Clock Timings Symbol T Clock period for PCI Clock PERIODPCICLK T PCI Clock high time CLKHIGH T PCI Clock low time CLKLOW Rise and fall time T RISE/FALL requirements for PCI Clock 5 ...

Page 95

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2 Bus Signal Timings The AC timing waveforms are shown in the following sections. 5.5.2.1 PCI Figure 16. PCI Output Timing CLK Output Delay Note 0 Figure 17. PCI Input Timing CLK Input Datasheet ...

Page 96

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 45. PCI Bus Signal Timings Symbol Clock to output for all bused signals. This is the PCI_AD[31:0], PCI_CBE_N [3:0], PCI_PAR, T PCI_FRAME_N, PCI_IRDY_N, clk2outb PCI_TRDY_N, PCI_STOP_N, PCI_DEVSEL_N, PCI_PERR_N, PCI_SERR_N Clock to output for all point-to-point T signals ...

Page 97

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.3 UTOPIA-2 Figure 18. UTOPIA-2 Input Timings Clock Signals Table 46. UTOPIA-2 Input Timings Values Symbol Input setup prior to rising edge of clock. Inputs included in this timing are UTP_IP_DATA[7:0], T setup UTP_IP_SOC, AND UTP_IP_FCI, and UTP_OP_FCI ...

Page 98

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.4 MII Figure 20. MII Output Timings eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs Table 48. MII Output Timings Values Symbol Clock to output delay for ETH_TXDATA and T 1 ETH_TXEN. ETH_TXDATA and ETH_TXEN hold time after ...

Page 99

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.5 MDIO Figure 22. MDIO Output Timings ETH_MDC ETH_MDIO Note: NPE is sourcing MDIO. Figure 23. MDIO Input Timings ETH_MDC ETH_MDIO Note: PHY is sourcing MDIO. Table 50. MDIO Timings Values Symbol ETH_MDIO, clock to output timing with respect to ...

Page 100

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.6 SDRAM Bus Figure 24. SDRAM Input Timings Clock Signals Table 51. SDRAM Input Timings Values Symbol Input setup prior to rising edge of clock. Inputs T included in this timing are SDM_DQ[31:0] (during setup a read operation). ...

Page 101

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.7 Expansion Bus Figure 26. Signal Timing With Respect to Clock Rising Edge EX_CLK EX_CS_N[0] EX_ADDR[23:0] EX_IOWAIT_N EX_RD_N EX_DATA[15:0] EX_WR_N EX_DATA[15:0] Table 53. Signal Timing With Respect to Clock Rising Edge Symbol setup ...

Page 102

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 27. Intel Multiplexed Read Mode ® Intel Multiplexed Read Mode 2-5 Cycles ALE Extended EX_CLK T EX_CS_N[0] alepulse EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N EX_DATA[15:0] Valid Address March 2005 102 Document Number: 252479, Revision: 005 ...

Page 103

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 28. Intel Multiplexed Write Mode ® Intel Multiplexed Write Mode 2-5 Cycles ALE Extended EX_CLK T EX_CS_N[0] alepulse EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_WR_N EX_DATA[15:0] Valid Address Datasheet Document Number: 252479, Revision: 005 ...

Page 104

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Table 54. Intel Multiplexed Mode Values Symbol Pulse width of EX_ALE (ADDR is valid at the rising edge of Talepulse EX_ALE) Tale2addrhold Valid address hold time after from falling edge of EX_ALE Tdval2valwrt Write data valid prior to EX_WR_N falling edge ...

Page 105

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Figure 29. Intel Simplex Read Mode ® Intel Simplex Read Mode EX_CLK EX_CS_N[0] EX_ADDR[23:0] EX_IOWAIT_N EX_RD_N EX_DATA[15:0] ® Figure 30. Intel Simplex Write Mode ® Intel Simplex Write Mode EX_CLK ...

Page 106

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 55. Intel Simplex Mode Values Symbol Parameter T Valid address to valid chip select addr2valcs T Write data valid prior to EX_WR_N falling edge dval2valwrt T Pulse width of the EX_WR_N wrpulse T Valid data after the rising edge of EX_WR_N ...

Page 107

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 31. Motorola* Multiplexed Read Mode Motorola* Multiplexed Read Mode 2-5 Cycles ALE Extended EX_CLK T EX_CS_N[0] alepulse EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] Valid Address Datasheet Document Number: 252479, Revision: 005 ...

Page 108

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 32. Motorola* Multiplexed Write Mode Motorola* Multiplexed Write Mode 2-5 Cycles ALE Extended EX_CLK T EX_CS_N[0] alepulse EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] March 2005 108 Document Number: 252479, Revision: 005 ...

Page 109

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 56. Motorola* Multiplexed Mode Values Symbol Parameter Pulse width of EX_ALE (ADDR is valid at the rising edge of T alepulse EX_ALE) T Valid address hold time after from falling edge of EX_ALE ale2addrhold T Write data valid prior to EXP_MOT_DS_N falling edge ...

Page 110

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 33. Motorola* Simplex Read Mode Motorola* Simplex Read Mode EX_CLK EX_CS_N[0] EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] March 2005 110 Document Number: 252479, Revision: 005 1-4 Cycles ...

Page 111

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 34. Motorola* Simplex Write Mode Motorola* Simplex Write Mode EX_CLK EX_CS_N[0] EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] Datasheet Document Number: 252479, Revision: 005 1-4 Cycles 1-4 Cycles 1-16 Cycles ...

Page 112

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 57. Motorola* Simplex Mode Values Symbol T Valid address to valid chip select ad2valcs T Write data valid prior to EXP_MOT_DS_N falling edge dval2valds T Pulse width of the EXP_MOT_DS_N dspulse T Valid data after the rising edge of EXP_MOT_DS_N ...

Page 113

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 35. HPI-8 Mode Read Accesses Datasheet Document Number: 252479, Revision: 005 March 2005 113 ...

Page 114

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 36. HPI-8 Mode Write Accesses March 2005 114 Document Number: 252479, Revision: 005 Datasheet ...

Page 115

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 58. HPI Timing Symbol Description State Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the ® ...

Page 116

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 59. HPI-8 Mode Write Access Values Symbol Data valid prior to the rising edge of the HDS1 data T data_setup strobe. T Data valid after the rising edge of the HDS1 data strobe. data_hold ...

Page 117

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 60. HPI-16 Multiplexed Write Accesses Values Symbol Valid time that address is asserted on the line. The address T add_setup is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data ...

Page 118

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 37. HPI-16 Multiplexed Write Mode March 2005 118 Document Number: 252479, Revision: 005 Datasheet ...

Page 119

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 61. HPI-16 Multiplexed Read Accesses Values Symbol Valid time that address is asserted on the line. The address T add_setup is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data ...

Page 120

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 38. HPI-16 Multiplex Read Mode March 2005 120 Document Number: 252479, Revision: 005 Datasheet ...

Page 121

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 62. HPI-16 Simplex Read Accesses Values Symbol Valid time that address is asserted on the line. The address is T add_setup asserted at the same time as chip select. Delay from chip select being active and the HDS1 data strobe ...

Page 122

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 39. HPI-16 Simplex Read Mode March 2005 122 Document Number: 252479, Revision: 005 Datasheet ...

Page 123

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 63. HPI-16 Simplex Write Accesses Values Symbol Valid time that address is asserted on the line. The address T add_setup is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data ...

Page 124

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 40. HPI-16 Simplex Write Mode March 2005 124 Document Number: 252479, Revision: 005 Datasheet ...

Page 125

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.7.1 EX_IOWAIT_N The EX_IOWAIT_N signal is available to be shared by devices attached to Chip Selects 0 through 7 and is used as required by slow devices. If the external device asserts EX_IOWAIT_N during the strobe phase of a read transfer, the controller will hold in that phase until the EX_IOWAIT_N goes false ...

Page 126

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 64. High-Speed, Serial Timing Values Symbol Setup time of HSS_TXFRAME, HSS_RXFRAME, and T1 HSS_RXDATA prior to the rising edge of clock Hold time of HSS_TXFRAME, HSS_RXFRAME, and T2 HSS_RXDATA after the rising edge of clock Setup time of HSS_TXFRAME, HSS_RXFRAME, and ...

Page 127

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.2.9 JTAG Figure 42. Boundary-Scan General Timings JTG_TMS, JTG_TDI Figure 43. Boundary-Scan Reset Timings Table 65. Boundary-Scan Interface Timings Values Symbol T JTAG_TCK low time bscl T JTAG_TCK high time bsch JTAG_TDI, JTAG_TMS setup time ...

Page 128

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.5.3 Reset Timings Figure 44. Reset Timings March 2005 128 Document Number: 252479, Revision: 005 Datasheet ...

Page 129

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 66. Reset Timings Table Parameters Symbol T RELEASE_PWRON_RST_N T RELEASE_RESET_IN_N T PLL_LOCK T EX_ADDR_SETUP T EX_ADDR_HOLD T WARM_RESET Notes RELEASE_PWRON_RST_N external oscillator is being used in place of a crystal, the 500-ms delay is not required. 2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be active until PLL_LOCK is active ...

Page 130

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Figure 45. Power-Up Sequence Timing March 2005 130 Document Number: 252479, Revision: 005 T POWER_UP Time V CCP V CC B2263-01 Datasheet ...

Page 131

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 5.7 I and Total Average Power CC Table 67. I and Total Average Power – Commercial Temperature Range CC Speed 266 MHz 400 MHz 533 MHz Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon samples ...

Page 132

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Table 68. I and Total Average Power – Extended Temperature Range CC Speed 266 MHz 400 MHz 533 MHz Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXCDP1100 Development Platform at room temperature using typical SKU silicon samples ...

Page 133

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor 6.0 Ordering Information For ordering information, please contact your local Intel sales representative. Datasheet Document Number: 252479, Revision: 005 March 2005 133 ...

Page 134

... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor This page is intentionally left blank. March 2005 134 Document Number: 252479, Revision: 005 Datasheet ...

Related keywords