gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 115

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Table 58.
Table 59.
Datasheet
HPI Timing Symbol Description
HPI-8 Mode Write Access Values
Notes:
1.
2.
3.
4.
5.
6.
7.
Notes:
1.
2.
3.
4.
5.
6.
7.
T
T
T
Intel
Symbol
cs2hds1val
hds1_pulse
add_setup
State
T1
T2
T3
T4
T5
®
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel
IXP42X Product Line and Intel
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel
IXP42X Product Line and Intel
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
®
IXP42X Product Line and Intel
IXP42X Product Line and Intel
Valid time that address is asserted on the line. The
address is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe
Document Number: 252479, Revision: 005
Setup/Chip Select Timing
Recovery Phase
Address Timing
Strobe Timing
Description
Hold Timing
®
Parameter
®
IXC1100 Control Plane processors has had sufficient time to
IXC1100 Control Plane processors has had sufficient time to
®
®
IXC1100 Control Plane processors has had sufficient time to
IXC1100 Control Plane processors has had sufficient time to
Min.
3
3
2
3
2
Max.
16
17
4
4
4
Min.
11
3
4
Cycles
Cycles
Cycles
Cycles
Cycles
Unit
Max.
45
4
5
Cycles
Cycles
Cycles
Units
March 2005
Notes
1, 5,
3, 5,
2,
6
6
6
Notes
1, 5,
2, 4,
6
6
5,
115
®
6
®
6
5