gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 96

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Intel
Table 45.
5.5.2.2
March 2005
96
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PCI Bus Signal Timings
USB Interface
For timing parameters, see the USB 1.1 specification. The IXP42X product line and IXC1100
control plane processors’ USB 1.1 interface is a device or function controller only. The IXP42X
product line and IXC1100 control plane processors’ USB v 1.1 interface cannot be line-powered.
T
T
T
T
T
T
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Symbol
clk2outb
clk2out
setupb
setup
rst-off
hold
See the timing measurement conditions.
Parts compliant to the 3.3 V signaling environment.
REQ# and GNT# are point-to-point signals and have different output valid delay and input setup
times than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has
a setup of 12 ns for 33 MHz and 5 ns for 66 MHz.
RST# is asserted and de-asserted asynchronously with respect to CLK.
All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
Setup time applies only when the device is not driving the pin. Devices cannot drive and receive
signals at the same time.
Timing was tested with a 70-pF capacitor to ground.
For additional information, see the PCI Local Bus Specification, Rev. 2.2.
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
Clock to output for all point-to-point
signals. This is the PCI_GNT_N
and PCI_REQ_N(0) only.
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
Input setup time for all point-to-
point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
Input hold time from clock.
Reset active-to-output float delay
Document Number: 252479, Revision: 005
Parameter
10, 12
Min.
2
2
7
0
33 MHz
Max.
11
12
40
Min.
1
1
3
5
0
66 MHz
Max.
40
6
6
Units
ns
ns
ns
ns
ns
ns
Datasheet
1, 2, 5,
1, 2, 5,
4, 6, 7,
5, 6, 7,
Notes
4, 7,
4, 7,
7,
7,
8
8
8
8
8
8