gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 34

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Intel
Table 6.
March 2005
34
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
SDRAM Interface (Sheet 1 of 2)
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_CLKOUT
SDM_BA[1:0]
SDM_RAS_N
SDM_CAS_N
SDM_CS_N[1:0]
SDM_WE_N
1.
2.
†
•
•
•
•
•
•
•
•
•
•
•
•
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Name
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see
—
—
—
—
—
—
—
—
—
—
—
—
High-Speed, Serial Interface 0
High-Speed, Serial Interface 1
MII Interfaces
UTOPIA-2 Interface
Expansion Bus Interface
UART Interfaces
USB Interface
Oscillator Interface
GPIO Interface
JTAG Interface
System Interface††
Power Interface
Document Number: 252479, Revision: 005
Reset
Power
on
Z
Z
Z
Z
Z
Z
Z
Z
1
Reset
0
1
0
0
1
1
1
1
signals
signals
signals
signals
2
signals
signals
Type
signals
signals
I/O
O
O
O
O
O
O
O
signals
†
Table 5 on page
signals
SDRAM Address: A0-A12 signals are output during the
READ/WRITE commands and ACTIVE commands to select a
location in memory to act upon.
SDRAM Data: Bidirectional data bus used to transfer data to
and from the SDRAM
SDRAM Clock: All SDRAM input signals are sampled on the
rising edge of SDM_CLKOUT. All output signals are driven
with respect to the rising edge of SDM_CLKOUT.
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the
bank the current command is attempting to access.
SDRAM Row Address strobe/select (active low): Along with
SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDRAM Column Address strobe/select (active low): Along
with SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDRAM Chip select (active low): CS# enables the command
decoder in the external SDRAM when logic low and disables
the command decoder in the external SDRAM when logic
high.
SDRAM Write enable (active low): Along with SDM_CAS_N,
SDM_RAS_N, and SDM_CS_N signals determines the
current command to be executed.
signals
signals
33.
Description
Datasheet