gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 38

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Intel
Table 8.
March 2005
38
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
High-Speed, Serial Interface 0
HSS_TXFRAME0
HSS_TXDATA0
HSS_TXCLK0
HSS_RXFRAME0
HSS_RXDATA0
HSS_RXCLK0
1.
2.
†
Name
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see
Document Number: 252479, Revision: 005
Reset
Power
On
Z
Z
Z
Z
Z
Z
1
Reset
VI
Z
Z
Z
Z
Z
2
Type
O/D
I/O
I/O
I/O
I/O
I
†
Table 5 on page
The High-Speed Serial (HSS) transmit frame signal can be
configured as an input or an output to allow an external
source become synchronized with the transmitted data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled low with a 10-K: resistor when not being
utilized in the system.
Transmit data out. Open Drain output.
Must be pulled high with a 10-K: resistor to V
The High-Speed Serial (HSS) transmit clock signal can be
configured as an input or an output. The clock can be a
frequency ranging from 512 KHz to 8.192 MHz. Used to clock
out the transmitted data. Configured as an input upon reset.
Frame sync and data can be selected to be generated on the
rising or falling edge of the transmit clock.
Should be pulled low with a 10-K: resistor when not being
utilized in the system.
The High-Speed Serial (HSS) receive frame signal can be
configured as an input or an output to allow an external
source to become synchronized with the received data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled low with a 10-K: resistor when not being
utilized in the system.
Receive data input. Can be sampled on the rising or falling
edge of the receive clock.
Should be pulled low through a 10-K: resistor when not
being utilized in the system.
The High-Speed Serial (HSS) receive clock signal can be
configured as an input or an output. The clock can be from
512 KHz to 8.192 MHz. Used to sample the received data.
Configured as an input upon reset.
Should be pulled low with a 10-K: resistor when not being
utilized in the system.
33.
Description
CCP
Datasheet
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