gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 24

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Intel
2.1.8
2.1.9
March 2005
24
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
The maximum burst size supported to the SDRAM interface is eight 32-bit words. This burst size
allows the best efficiency/fairness performance between accesses from the North AHB and the
South AHB.
Expansion Bus
The expansion interface allows easy and — in most cases — glue-less connection to peripheral
devices. It also provides input information for device configuration after reset. Some of the
peripheral device types are flash, ATM control interfaces, and DSPs used for voice applications.
(Some voice configurations can be supported by the HSS interfaces and the Intel XScale
implementing voice-compression algorithms.)
The expansion bus interface is a 16-bit interface that allows an address range of 512 bytes to
16 Mbytes, using 24 address lines for each of the eight independent chip selects.
Accesses to the expansion bus interface consists of five phases. Each of the five phases can be
lengthened or shortened by setting various configuration registers on a per-chip-select basis. This
feature allows the IXP42X product line and IXC1100 control plane processors to connect to a wide
variety of peripheral devices with varying speeds.
The expansion bus interface supports Intel or Motorola* microprocessor-style bus cycles. The bus
cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for
each of the eight chip-selects.
Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments HPI-8 or
HPI-16 style accesses for DSPs.
The expansion bus interface is an asynchronous interface to externally connected chips. However,
a clock must be supplied to the IXP42X product line and IXC1100 control plane processors’
expansion bus interface for the interface to operate. This clock can be driven from GPIO 15 or an
external source. The maximum clock rate that the expansion bus interface can accept is
66.66 MHz.
At the de-assertion of reset, the 24-bit address bus is used to capture configuration information
from the levels that are applied to the pins at this time. External pull-up/pull-down resistors are
used to tie the signals to particular logic levels. (For additional details, see
Information” on page
High-Speed, Serial Interfaces
The high-speed, serial interfaces are six-signal interfaces that support serial transfer speeds from
512 KHz to 8.192 MHz, for some models of the IXP42X product line and IXC1100 control plane
processors. (See
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the
IXP42X product line and IXC1100 control plane processors. The high-speed, serial interfaces are
capable of supporting various protocols, based on the implementation of the code developed for the
network processor engine core. For a list of supported protocols, see the Intel
Programmer’s Guide.
Table 4 on page
Document Number: 252479, Revision: 005
50.)
20.)
“Package and Pinout
®
IXP400 Software
Datasheet
®
Core,