gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 97
gwixp425bdt
Manufacturer Part Number
gwixp425bdt
Description
Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
Manufacturer
Intel Corporation
Datasheet
1.GWIXP425BDT.pdf
(134 pages)
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5.5.2.3
Figure 18.
Table 46.
Figure 19.
Table 47.
Datasheet
UTOPIA-2
UTOPIA-2 Input Timings
UTOPIA-2 Input Timings Values
UTOPIA-2 Output Timings
UTOPIA-2 Output Timings Values
Note:
1.
Symbol
Symbol
T
T
T
Intel
T
clk2out
holdout
setup
hold
Signals
®
Signals
Timing was tested with a 70-pF capacitor to ground.
Clock
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Clock
Input setup prior to rising edge of clock. Inputs
included in this timing are UTP_IP_DATA[7:0],
UTP_IP_SOC, AND UTP_IP_FCI, and
UTP_OP_FCI.
Input hold time after the rising edge of the clock.
Inputs included in this timing are
UTP_IP_DATA[7:0], UTP_IP_SOC, and
UTP_IP_FCI, and UTP_OP_FCI.
Rising edge of clock to signal output. Outputs
included in this timing are UTP_IP_DATA[3:0],
UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
UTP_IP_DATA[3:0], UTP_OP_SOC,
UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
Document Number: 252479, Revision: 005
Parameter
Parameter
Tclk2out
Tsetup
Thold
Tholdout
Min.
Min.
8
1
1
Max.
Max.
17
Units
Units
ns
ns
ns
ns
A9579-01
March 2005
A9578-01
Notes
Notes
1
1
97
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