gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 40

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Intel
Table 10.
March 2005
40
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
MII Interfaces (Sheet 1 of 2)
ETH_TXCLK0
ETH_TXDATA0[3:0]
ETH_TXEN0
ETH_RXCLK0
ETH_RXDATA0[3:0]
ETH_RXDV0
ETH_COL0
ETH_CRS0
ETH_MDIO
1.
2.
†
Name
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.
After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of
PLL_LOCK, all signals reflect the value shown in the RESET column.
For a legend of the Type codes, see
Document Number: 252479, Revision: 005
Reset
Power
On
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
Reset
VI
VI
VI
VI
VI
VI
0
0
Z
2
Type
I/O
O
O
I
I
I
I
I
I
Table 5 on page
†
Externally supplied transmit clock.
Should be pulled low through a 10-K: resistor when not
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK0.
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK0, at the first nibble of the preamble and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
Should be pulled low through a 10-K: resistor when not
being utilized in the system.
Receive data bus from PHY, data sampled synchronously
with respect to ETH_RXCLK0
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data. Should be pulled low
through a 10-K: resistor when not being utilized in the
system.
Asserted by the PHY when a collision is detected by the
PHY. Should be pulled low through a 10-K: resistor when
not being utilized in the system.
Asserted by the PHY when the transmit medium or receive
medium is active. De-asserted when both the transmit and
receive medium are idle. Remains asserted throughout the
duration of a collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously, with
respect to ETH_RXCLK0. Should be pulled low through a
10-K: resistor when not being utilized in the system.
Management data output. Provides the write data to both
PHY devices connected to each MII interface.
An external 1.5-K: pull-up resistor is required.
Note:
Should be pulled low through a 10-K: resistor when not
being utilized in the system.
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• Should be pulled low through a 10-K: resistor when
not being utilized in the system.
If interfacing with a single Intel
Transceiver, and a 1.5K pull-up resistor is not used, the
NPE will ‘see’ 32 PHYs on the MII interface.
33.
Description
®
LXT972 Fast Ethernet
Datasheet