gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 129

• Manufacturer Part Number: gwixp425bdt
• Description: Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
• Manufacturer: Intel Corporation

Table 66.
5.6
Datasheet
Reset Timings Table Parameters
Power Sequence
The 3.3-V I/O voltage (V
IXP42X product line and IXC1100 control plane processors’ core voltage (V
become stable prior to the 3.3-V I/O voltage (V
voltages follow the V
value for T
V
line and IXC1100 control plane processors.
T
T
T
T
T
T
Notes:
1.
2.
3.
RELEASE_PWRON_RST_N
RELEASE_RESET_IN_N
PLL_LOCK
EX_ADDR_SETUP
EX_ADDR_HOLD
WARM_RESET
CCP
Intel
at 3.3 V and V
®
Symbol
T
external oscillator is being used in place of a crystal, the 500-ms delay is not required.
The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a
programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals
must be active until PLL_LOCK is active.
PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is
asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks
after the watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
RELEASE_PWRON_RST_N
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
POWER_UP
Document Number: 252479, Revision: 005
CC
CC
must be at least 1
Minimum time required to hold the
PWRON_RST_N at logic 0 state after
stable power has been applied to the
IXP42X product line and IXC1100 control
plane processors. When using a crystal
to drive the processors’ system clock.
(OSC_IN and OSC_OUT)
Minimum time required to hold the
RESET_IN_N at logic 0 state after
PWRON_RST_N has been released to a
logic 1 state. The RESET_IN_N signal
must be held low when the
PWRON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to
drive to logic 1 after RESET_IN_N is
driven to logic 1 state. The boot
sequence does not occur until this period
is complete.
Minimum time for the EX_ADDR signals
to drive the inputs prior to RESET_IN_N
being driven to logic 1 state. This is used
for sampling configuration information.
Minimum/maximum time for the
EX_ADDR signals to drive the inputs
prior to PLL_LOCK being driven to logic 1
state. This is used for sampling
configuration information.
Minimum time required to drive
RESET_IN_N signal to logic 0 in order to
cause a reset after the IXP42X product
line and IXC1100 control plane
processors has been in normal operation.
The power must remain stable and the
PWRON_RST_N signal must remain
stable.
at 1.3 V. There are no power-down requirements for the IXP42X product
power-up pattern. The V
CCP
) must be powered up 1
is the time required for the internal oscillator to reach stability. When an
Parameter
µ
s. The T
CCP
CCOSCP
POWER_UP
). The V
µs
before the core voltage (V
follows the V
CCOSC
timing parameter is measured from
Min.
500
500
10
50
0
, V
CCPLL1
Typ.
CCP
power-up pattern. The
, and V
Max.
CC
10
20
) must never
CC
CCPLL2
Units
). The
ms
µs
March 2005
ns
ns
ns
ns
Note
1
2
2
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