gwixp425bdt Intel Corporation, gwixp425bdt Datasheet - Page 100
gwixp425bdt
Manufacturer Part Number
gwixp425bdt
Description
Intel Xp42x Product Line Of Network Processors And Ixc1100 Control Plane Processor
Manufacturer
Intel Corporation
Datasheet
1.GWIXP425BDT.pdf
(134 pages)
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Intel
5.5.2.6
Figure 24.
Table 51.
Figure 25.
Table 52.
March 2005
100
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
SDRAM Bus
SDRAM Input Timings
SDRAM Input Timings Values
SDRAM Output Timings
SDRAM Output Timings Values
Note:
1.
Symbol
Symbol
T
T
T
T
clk2out
holdout
setup
Signals
hold
Clock
Timing test were performed with a 70-pF load to ground.
Input setup prior to rising edge of clock. Inputs
included in this timing are SDM_DQ[31:0] (during
a read operation).
Input hold time after the rising edge of the clock.
Inputs included in this timing are SDM_DQ[31:0]
(during a read operation).
Rising edge of clock-to-signal output. Outputs
included in this timing are SDM_ADDR[12:0],
SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE,
SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N,
SDM_RAS_N, SDM_DQ[31:0] (during a write
operation).
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
SDM_DQ[31:0] (during a write operation).
Signals
Clock
Document Number: 252479, Revision: 005
Parameter
Parameter
T setup
T clk2out
Data Valid
T hold
Min.
Min.
1.5
1.4
1.5
T holdout
Max.
Max.
5.5
Units
Units
ns
ns
ns
ns
Datasheet
A9584-01
Notes
4891-01
Notes
1
1
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