PEB2075 INFINEON [Infineon Technologies AG], PEB2075 Datasheet - Page 134

• Manufacturer Part Number: PEB2075
• Description: ICs for Communications Extended PCM Interface Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

OMDR
– The CM initialization mode (OMS1 … 0 = 10) allows fast programming of the
Since memory operations must be synchronized to the EPIC internal bus which is
clocked by the reference clock (RCL), the time required for an indirect register access
can be given as a multiple of RCL clock cycles. A “normal” access to a single memory
location, for example, takes a maximum of 9.5 RCL cycles which is approximately 2.4 s
assuming a 4 MHz clock (e.g. CFI configured as standard IOM-2 interface).
Memory Access Modes
Access to memory locations is furthermore influenced by the operation mode set via the
Operation Mode Register OMDR. There are 4 modes which can be selected with the
OMDR:OMS1, OMS0 bits:
Operation Mode Register
– The CM reset mode (OMS1 … 0 = 00) is used to reset all locations of the control
– In the normal operation mode (OMS1 … 0 = 11) the CFI and PCM interfaces are
– In test mode (OMS1 … 0 = 01) the EPIC sustains normal operation. However
Semiconductor Group
memory code and data fields with a single command within only 256 RCL cycles. A
typical application is resetting the CM with the command MACR = 70
the contents of MADR (XX
(unassigned channel) to all code field locations. A CM reset should be made after
each hardware reset. In the CM reset mode the EPIC does not operate normally i.e.
the CFI and PCM interfaces are not operational.
Control Memory since each memory access takes a maximum of only 2.5 RCL cycles
compared to the 9.5 RCL cycles in the normal mode. Accesses are performed on
individual addresses specified by MAAR. The initialization of control/signaling
channels in IOM or SLD applications can, for example, be carried out in this mode
(see chapter 5.5.1). In the CM initialization mode the EPIC does also not work
normally.
operational. Memory accesses performed on single addresses (specified by MAAR)
take 9.5 RCL cycles. An initialization of the complete data memory tristate field takes
1035 RCL cycles.
memory accesses are no longer performed on a specific address defined by MAAR,
but on all locations of the selected memory, the contents of MAAR (including the U/D
bit!) being ignored. This function can for example be used to program a PCM idle code
to all PCM ports and time slots with a single command.
bit 7
OMS1
OMS0
PSB
H
) to all data field locations and the code “0000”
read/write
PTL
134
COS
reset value:
MFPS
Application Hints
CSB
H
00
which writes
PEB 2055
H
PEF 2055
bit 0
RBS