PEB2075 INFINEON [Infineon Technologies AG], PEB2075 Datasheet - Page 42

• Manufacturer Part Number: PEB2075
• Description: ICs for Communications Extended PCM Interface Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

3.5.2.1 Register Initialization
The PCM and CFI configuration registers (PMOD, PBNR,
be programmed to the values required for the application. The correct setting of the PCM
and CFI registers is important in order to obtain a reference clock (RCL) which is
consistent with the externally applied clock signals.
The state of the operation mode (OMDR:OMS1..0 bits) does not matter for this
programming step.
3.5.2.2 Control Memory Reset
Since the hardware reset does not affect the EPIC memories (Control and Data
Memories), it is mandatory to perform a “software reset” of the CM. The CM code
“0000”
OMDR:OMS1..0 must be to “00”
The resetting of the complete CM takes 256 RCL clock cycles. During this time, the
STAR:MAC-bit is set to logical “1”.
3.5
For proper initialization of the EPIC the following procedure is recommended:
3.5.1
A reset pulse can be applied at the RES pin for at least 4 PDC clock cycles. The reset
pulse sets all registers to their reset values (refer to chapter 4.1).
Note: In this state DCL and FSC do not provide any clock signals.
3.5.2
written to the CM data field is then don’t care, e.g. FF
Semiconductor Group
B
Initialization Procedure
Hardware Reset
EPIC
(unassigned channel) should be written to each location of the CM. The data
PMOD =
PBNR
POFD
POFU
PCSR
CMD1
CMD2
CBNR
CTAR
CBSR
CSCR
MADR =
MACR =
Wait for STAR:MAC = “0”
®
Initialization
=
=
=
=
=
=
=
=
=
=
PCM-mode, timing characteristics, etc.
Number of bits per PCM-frame
PCM-offset downstream
PCM-offset upstream
PCM-timing
CFI-mode, timing characteristics, etc.
CFI-timing
Number of bits per CFI-frame
CFI-offset (time slots)
CFI-offset (bits)
CFI-sub channel positions
FF
70
H
H
B
for this procedure (reset value).
42
H
.
, CMD1, CMD2,
Operational Description
PEB 2055
PEF 2055
) have to