PEB2075 INFINEON [Infineon Technologies AG], PEB2075 Datasheet - Page 176

• Manufacturer Part Number: PEB2075
• Description: ICs for Communications Extended PCM Interface Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

PEB 2055
PEF 2055
Application Hints
5.5.1
Initialization of Preprocessed Channels
The initialization of preprocessed channels is usually performed after the CM reset
sequence during device initalization. Resetting the CM sets all CFI time slots to
unassigned channels (CM code ‘0000’). The initialization of preprocessed channels
consists of writing appropriate CM codes to those CFI time slots that should later be
handled by the CS or MF handler.
The initialization or re-initialization of preprocessed channels can of course also be
carried out during the operational phase of the device.
If the CFI shall be operated as a standard IOM-2 interface, for example, the CFI frame
consists of 32 time slots, numbered from 0 to 31 (see figure 22).
The B channels occupy time slots 0 and 1 (IOM channel 0), 4 and 5 (IOM channel 1), 8
and 9 (IOM channel 2), and so on. The B channels are normally switched to the PCM
interface and are programmed only if the actual switching function is required.
The monitor, D and C/I channels occupy time slots 2 and 3 (IOM channel 0), 6 and 7
(IOM channel 1), 10 and 11 (IOM channel 2), and so on. These time slots must be
initialized in both upstream and downstream directions for the desired functionality. In
order to speed up this initialization, the EPIC can be set into the CM initialization mode
as described in chapter 5.3.2.
There are several options available to cover the different applications like switched D
channel, 6 bit signaling, etc. It should be noted that each pair of time slots can
individually be set for a specific application and that the up- and downstream directions
can also be set differently, if required.
Decentral D-Channel Handling Scheme
This option applies for IOM channels where the even time slot consists of an 8 bit
monitor channel and the odd time slot of a 2 bit D-Channel followed by a 4 bit C/I channel
followed by the 2 monitor handshake bits MR and MX.
The monitor channel is handled by the MF handler according to the selection of
handshake or non-handshake protocol. If the handshake option is selected (IOM-2), the
MF handler controls the MR and MX bits according to the IOM-2 specification. If the no
handshake option is selected (IOM-1), the MF handler sets both MR and MX bits to
logical 1; the MR and MX bit positions can then, if required, be accessed together with
the 4 bit C/I field via the even control memory address.
The D-Channel is not processed at all, i.e. the input in upstream direction is ignored and
the output in downstream direction is set to high impedance. External D-Channel
controllers, e.g. 2
IDECs PEB 2075, can then be connected to each IOM interface in
order to realize decentral D-Channel processing.
The 4 bit C/I channel can be accessed by the µP for controlling layer-1 devices. In
upstream direction each change in the C/I value is reported by interrupt to the µP and the
CFI time slot address is stored in the CIFIFO (refer to chapter 5.5.2). A C/I change is
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