PEB2075 INFINEON [Infineon Technologies AG], PEB2075 Datasheet - Page 167

• Manufacturer Part Number: PEB2075
• Description: ICs for Communications Extended PCM Interface Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

PEB 2055
PEF 2055
Application Hints
The exact respective time slot positions where the delay skips from 0 frames to 1 frame
and from 1 frame to 2 frames can be determined when having a closer look at the internal
read and write cycles to the Data Memory.
The next two figures show the internal timing characteristics for the access to the data
memory (DM) of the EPIC. For simplicity, only the case where the PCM and CFI frames
both start simultaneously at position “time slot 0, bit 7” is shown. Also, only the cases
with 2, 4 and 8
1024 kbit/s data rates are shown. All other cases (different frame offsets
and different data rates) can, however, be deduced by taking into account the respective
frame positions, and, eventually, by taking into account a different RCL frequency.
5.4.4.1 Internal Procedures at the Serial Interfaces
The data is received and transmitted at the PCM and configurable interfaces in a serial
format. Before being written to the DM, the data is converted into parallel format. The
vertical arrows indicate the position in time where the incoming time slot data is written
to the data memory. The writing to the DM is only possible during certain time intervals
which are also indicated in the figures. For outgoing time slots, the data is first read in
parallel format from the DM. This also is only possible during certain read cycles as
indicated in the figures (vertical arrows). Before the time slot data is sent out, it must first
be converted into serial format.
The data contained in a time slot can be switched from an incoming time slot position to
an outgoing time slot position within the same frame (0 frame delay) if the reading from
the DM occurs after the writing to the DM. If the reading occurs before the writing, the
data from the previous frame is taken, i.e. the frame delay is one frame.
Semiconductor Group
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