PEB2075 INFINEON [Infineon Technologies AG], PEB2075 Datasheet - Page 164

• Manufacturer Part Number: PEB2075
• Description: ICs for Communications Extended PCM Interface Controller
• Manufacturer: INFINEON [Infineon Technologies AG]

downstream CM (MAAR contains the encoding for the downstream CFI time slot (U/D =
0)). If the data should also be transmitted at DD# (transparent loop), the programming is
performed with MACR:CMC3 … 0 = 0001 … 0111, the actual code depending on the
required bandwidth. If DD# should be disabled (non-transparent loop), the programming
is performed with MACR:CMC3 … 0 = 0000, the code for unassigned channels.
The second connection switches the serial CFI time slot data back to the upstream PCM
time slot. This connection is programmed by writing the encoded PCM time slot via
MADR to the upstream CM. This “upstream” pointer must however have the MSB set
to 0 (U/D = 0). This MADR value is written to the same spare CFI time slot as the PCM
time slot had been switched to in the first step. Only that now the upstream CM is
accessed (MAAR addresses the upstream CFI time slot (U/D = 1)).
In contrast to the CFI
CFI data out of the upstream data memory (see chapter 5.4.3.1), the PCM
still points to the upstream data memory, i.e to an upstream PCM time slot.
The following example illustrates the necessary programming steps for establishing
PCM to PCM loops:
Example
In PCM mode 1 and CFI mode 0 the following non-transparent PCM to PCM loop via CFI
port 1, time slot 4 shall be programmed:
Downstream: CFI port 1, time slot 4, bits 7 … 0 from PCM port 0, time slot 13, bits 7 … 0
W:MADR
W:MAAR
W:MACR
5.4.3.2 PCM - PCM Loops
For looping back a time slot of a PCM input port to a PCM output port, two connections
must be programmed:
The first connection switches the downstream PCM time slot to a spare CFI time slot.
This connection is programmed like a normal PCM to CFI link, i.e the MADR contains
the encoding for the downstream PCM time slot (U/D = 0) which is written to the
PCM loop is realized differently:
The downstream PCM
downstream serial CFI output. From this internal output, the data is switched to the
upstream serial CFI input if the control memory of the corresponding upstream CFI time
slot contains a pointer with a leading 0 (U/D = 0). However, this pointer (with U/D = 0)
Semiconductor Group
= 0001 1001
= 0001 0010
= 0111 0000
PCM
B
B
B
CFI connection switches the PCM data to the internal
PCM time slot encoding (pointer to downstream DM)
CFI time slot encoding (address of downstream CM)
CM code for unassigned channel (0000)
CFI loop, which is internally realized by extracting the
164
Application Hints
PEB 2055
PEF 2055
CFI