LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 107

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
17.4.30 CR29
CR29 can only be accessed in the configuration state and after the CSR has been initialized to 29H.
17.4.31 CR2A – CR2E
17.4.32 CR2F – CR30
SMSC DS – LPC47N237
These registers are reserved, read only, and return 0 when read.
CR2F and CR30 can only be accessed in the configuration state and after the CSR has been initialized to
2FH and 30H. The CR2F and CR30 are used to set the Runtime Register Block base address ADR[11:2].
The Runtime Register Block base address can be set to 960 locations on 4-byte boundaries from 100H –
FFCH. To disable Runtime Registers Block, set ADR11 – ADR8 to zero.
SCE Address Decoding: address bits A[15:12] must be ‘0000’ to access Runtime Register Block registers.
A[1:0] are decoded as XXb.
BIT NO.
0-6
7
Reserved
SIRQ_CLKRUN_E
N
Type: R/W
BIT NAME
Table 17.27 – UART Interrupt Operation
OUT2 bit
UART
0
1
1
0
0
1
1
1
1
Read Only. A read returns 0.
Serial IRQ and CLKRUN enable bit. 0 = Disable 1 = Enable
(default)
DATASHEET
UART
Table 17.28 – CR29
SIRQ_CLKRUN_En
Output State
de-asserted
de-asserted
de-asserted
UART IRQ
asserted
asserted
asserted
Page 107
Z
Z
Z
Pin State
DESCRIPTION
IRQ PIN
UART
Default: 0x80 on VCC POR
Z
Z
Z
1
0
1
1
0
0
Revision 0.3 (10-26-04)