LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 7

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
Chapter 21
21.1
21.2
21.3
21.4
Chapter 22
Figure 3.1 – LPC47N237 Pin Layout............................................................................................................................12
Figure 5.1 – LPC47N237 Block Diagram .....................................................................................................................20
Figure 8.1 - Serial Data ................................................................................................................................................33
Figure 11.1
Figure 11.2
Figure 12.1 – nCLKRUN System Implementation Example .........................................................................................73
Figure 12.2 – Clock Start Illustration ............................................................................................................................74
Figure 13.1 - GPIO Function Illustration.......................................................................................................................76
Figure 15.1 – SMBus Isolation Switch..........................................................................................................................83
Figure 15.2 - GPIO Transition Cases ...........................................................................................................................86
Figure 15.3 – Sample Representation of nSMBINT Assertion Logic ............................................................................88
Figure 20.1 - POWER-UP TIMING.............................................................................................................................122
Figure 20.2 – 24MHz_OUT CLOCK TIMING .............................................................................................................123
Figure 20.3 – PCI CLOCK TIMING ............................................................................................................................123
Figure 20.4 - RESET TIMING ....................................................................................................................................123
Figure 20.5 – Output Timing Measurement Conditions, LPC Signals ........................................................................124
Figure 20.6 – Input Timing Measurement Conditions, LPC Signals ...........................................................................124
Figure 20.7 – LPC I/O Write .......................................................................................................................................124
Figure 20.8 – LPC I/O Read.......................................................................................................................................125
Figure 20.9 – DMA Request Assertion Through nLDRQ............................................................................................125
Figure 20.10 – LPC DMA Write (First Byte) ...............................................................................................................125
Figure 20.11 – LPC DMA Read (First Byte) ...............................................................................................................125
Figure 20.12 – EPP 1.9 Data or Address Write Cycle ................................................................................................126
Figure 20.13 – EPP 1.9 Data or Address Read Cycle................................................................................................127
Figure 20.14 – EPP 1.7 Data or Address Write Cycle ................................................................................................128
Figure 20.15 – EPP 1.7 Data or Address Read Cycle................................................................................................128
Figure 20.16 – Parallel Port FIFO Timing...................................................................................................................130
Figure 20.17 - ECP Parallel Port Forward Timing ......................................................................................................131
Figure 20.18 - ECP Parallel Port Reverse Timing ......................................................................................................132
Figure 20.19 – SER_IRQ Setup and Hold Time.........................................................................................................133
Figure 20.20 – Serial Port Data..................................................................................................................................133
Figure 20.21 – SMBus Timing....................................................................................................................................134
Figure 21.1 – XNOR-CHAIN TEST STRUCTURE .....................................................................................................135
Figure 22.1 – 100 Pin TQFP Package Outline ...........................................................................................................138
Table 2.1 – LPC47N237 Pin Configuration ..................................................................................................................11
Table 4.1 – Pin Description ..........................................................................................................................................13
Table 7.1 - Super I/O Block Addresses ........................................................................................................................24
SMSC DS – LPC47N237
20.1.4
20.1.5
20.1.6
20.1.7
21.1.1
21.1.2
Entering and Exiting Test Mode................................................................................................... 135
Pin List of XNOR Chain ............................................................................................................... 136
Setup of XNOR Chain .................................................................................................................. 136
Testing Procedure........................................................................................................................ 136
Forward Data Transfer Phase ...........................................................................................................129
Reverse-Idle Phase...........................................................................................................................129
Reverse Data Transfer Phase...........................................................................................................129
Output Drivers ...................................................................................................................................130
XNOR-Chain test mode can be entered as follows: ..........................................................................135
XNOR-Chain test mode can be exited as follows:.............................................................................135
A. Start Frame timing with source sampled a low pulse on IRQ1.......................................................68
B. Stop Frame Timing with Host using 17 SER_IRQ sampling period ...............................................68
XNOR-Chain Test Mode.............................................................................................. 135
Package Outline ............................................................................................................ 138
DATASHEET
LIST OF FIGURES
LIST OF TABLES
Page 7
Revision 0.3 (10-26-04)