LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 26

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

7.3.2
Revision 0.3 (10-26-04)
The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification Revision
1.0.
I/O Read and Write Cycles
The LPC47N237 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO
accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes
is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times.
Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will
break it up into 8-bit transfers.
See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles
for the I/O Read and Write cycles.
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47N237. DMA write
cycles involve the transfer of data from the LPC47N237 to the host (main memory). Data will be coming
from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47N237 are 1
byte.
See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and
the sequence of the DMA Read and Write cycles.
DMA Protocol
DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47N237 and special
encodings on LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Specification Revision 1.0.
Power Management
CLOCKRUN Protocol
See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1 and “PCI CLKRUN Support”
section.
LPCPD Protocol
The LPC47N237 will function properly if the nLPCPD signal goes active and then inactive again without
nPCI_RESET becoming active. This is a requirement for notebook power management functions.
Although the LPC Bus spec 1.0 section 8.2 states, "After nLPCPD goes back inactive, the LPC I/F will
always be reset using LRST#”, this statement does not apply for mobile systems. LRST# (nPCI_RESET)
will not occur if the LPC Bus power was not removed. For example, when exiting a "light" sleep state
(ACPI S1, APM POS), LRST# (nPCI_RESET) will not occur. When exiting a "deeper" sleep state (ACPI
S3-S5, APM STR, STD, soft-off), LRST# (nPCI_RESET) will occur.
The nLPCPD pin is implemented as a “local” powergood for the LPC bus in the LPC47N237. It is not used
as a global powergood for the chip. It is used to reset the LPC block and hold it in reset.
DATASHEET
Page 26
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS – LPC47N237