LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 99

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
17.4.11 CR0B
17.4.12 CR0C
17.4.13 CR0D
17.4.14 CR0E
17.4.15 CR0F
SMSC DS – LPC47N237
This register is reserved, read only, and returns 0 when read.
CR0C can only be accessed in the configuration state and after the CSR has been initialized to 0CH.
CR0C controls the operating mode of the UART. This register is reset to the default state by a POR or a
hardware reset.
CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This
register is read only. CR0D contains the LPC47N237 Device ID. This register is hardwired to 13H.
CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This
register is read only. CR0E contains the current LPC47N237 Chip Revision Level starting at 00H.
CR0F can only be accessed in the configuration state and after the CSR has been initialized to 0FH.
CR0F is a test control register and all bits must be treated as Reserved.
BIT NO.
BIT NO.
4-7
0-5
0
1
2
3
6
7
UART Speed
Type: R/W
Type: R/W
BIT NAME
BIT NAME
Reserved
Reserved
Reserved
THR0
THR1
THR2
THR3
ECP FIFO Threshold/IR MUX
ECP FIFO Threshold 0.
ECP FIFO Threshold 1.
ECP FIFO Threshold 2.
ECP FIFO Threshold 3.
Read Only. A read returns 0.
Read Only. A read returns 0.
This bit enables the high speed mode of UART.
1 = High speed enabled
0 = Standard (default)
Read Only. A read returns 0.
DATASHEET
Table 17.10 – CR0C
Table 17.9 – CR0A
UART Mode
Page 99
Default: 0x00 on VCC POR and HARD RESET
DESCRIPTION
DESCRIPTION
Bits[7:6] = 00 on HARD RESET
Default: 0x00 on VCC POR;
Revision 0.3 (10-26-04)