LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 25

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
7.3.1
SMSC DS – LPC47N237
LAD[3:0]
nLFRAME
nPCI_RESET
nLDRQ
nIO_PME
nLPCPD
SER_IRQ
PCI_CLK
nCLKRUN
SIGNAL NAME
I/O Write
I/O Read
DMA Write
DMA Read
LPC Interface Signal Definition
The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI
33MHz electrical signal characteristics.
LPC Cycles
The following cycle types are supported by the LPC protocol.
The LPC47N237 ignores cycles that it does not support.
Field Definitions
The data transfers are based on specific fields that are used in various combinations, depending on the
cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and
data information over the LPC bus between the host and the LPC47N237. See the Low Pin Count (LPC)
Interface Specification Revision 1.0 from Intel, Section 4.2 for definition of these fields.
nLFRAME Usage
nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort
or time-out condition. This signal is to be used by the LPC47N237 to know when to monitor the bus for a
cycle.
This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start
or stop of a cycle, and that the LPC47N237 monitors the bus to determine whether the cycle is intended for
it. The use of nLFRAME allows the LPC47N237 to enter a lower power state internally. There is no need
for the LPC47N237 to monitor the bus when it is inactive, so it can decouple its state machines from the
bus, and internally gate its clocks.
When the LPC47N237 samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on
the next clock and monitor the bus for new cycle information.
I/O
Output
OD
Input
Input
Input
I/O
Input
I/OD
CYCLE TYPE
TYPE
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
PCI Reset. Used as LPC Interface Reset.
Encoded DMA/Bus Master request for the LPC interface.
Power Mgt Event signal. Allows the LPC47N237 to request wakeup.
Powerdown Signal. Indicates that the LPC47N237 should prepare for power to be
shut on the LPC interface.
Serial IRQ.
PCI Clock.
Clock Run. Allows the LPC47N237 to request the stopped PCI_CLK be started.
DATASHEET
1 Byte
1 Byte
1 Byte
1 Byte
Page 25
DESCRIPTION
TRANSFER SIZE
Revision 0.3 (10-26-04)