LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 27

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS – LPC47N237
An internal powergood is implemented in LPC47N237 to minimize power dissipation in the entire chip.
Prior to going to a low-power state, the system will assert the nLPCPD signal. It will go active at least 30
microseconds prior to the LCLK# (PCI_CLK) signal stopping low and power being shut to the other LPC I/F
signals.
Upon recognizing nLPCPD active, the LPC47N237 will drive the nLDRQ signal low or tri-state, and do so
until nLPCPD goes back active.
Upon recognizing nLPCPD inactive, the LPC47N237 will drive its nLDRQ signal high.
See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.
SYNC Protocol
See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a table of valid SYNC
values.
Typical Usage
The SYNC pattern is used to add wait states. For read cycles, the LPC47N237 immediately drives the
SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If
the LPC47N237 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready,
at which point it will drive 0000 or 1001. The LPC47N237 will choose to assert 0101 or 0110, but not
switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.
The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete
within a few clocks. The LPC47N237 uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided
for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the
LPC47N237 uses a SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
SYNC Timeout
The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC
pattern, it will abort the cycle.
The LPC47N237 does not assume any particular timeout. When the host is driving SYNC, it may have to
insert a very large number of wait states, depending on PCI latencies and retries.
SYNC Patterns and Maximum Number of SYNCS
If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.
If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47N237 has
protection mechanisms to complete the cycle. This is used for EPP data transfers and will utilize the same
timeout protection that is in EPP.
DATASHEET
Page 27
Revision 0.3 (10-26-04)