LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 29

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
Chapter 8
8.1
Note 8.1 DLAB is Bit 7 of the Line Control Register
8.1.1
SMSC DS – LPC47N237
The LPC47N237 incorporates a full function UART. They are compatible with the 16450, the 16450 ACE
registers and the 16C550A. The UART perform serial-to-parallel conversion on received characters and
parallel-to-serial conversion on transmit characters. The data rates are independently programmable from
460.8K baud down to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits;
even, odd, sticky or no parity; and prioritized interrupts. The UART contains a programmable baud rate
generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. The UART is
also capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on
disabling, power down and changing the base address of the UARTs. The interrupt from a UART is
enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's
interrupt.
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
ports are defined by the configuration registers (see Configuration section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses. The LPC47N237 serial port
register set is described below.
The following section describes the operation of the registers.
Receive Buffer Register (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted
and received first. Received data is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register.
The shift register is not accessible.
(NOTE 8.1)
DLAB
0
0
0
X
X
X
X
X
X
X
1
1
Serial Port (UART)
A2
0
0
0
0
0
0
1
1
1
1
0
0
Table 8.1 - Addressing the Serial Port
A1
DATASHEET
0
0
0
1
1
1
0
0
1
1
0
0
A0
0
0
1
0
0
1
0
1
0
1
0
1
Page 29
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
REGISTER NAME
Revision 0.3 (10-26-04)