LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 51

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
Notes:
9.4
9.5
SMSC DS – LPC47N237
SPP and EPP can use 1 common register.
nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP
read cycles, PCD is required to be a low.
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
SIGNAL
4.
5.
6.
7.
8.
9.
Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost
peripherals Maintains link and data layer separation Permits the use of active output drivers permits the
use of adaptive signal timing Peer-to-peer capability.
Vocabulary
The following terms are used in this document:
Assert:
EPP
If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination
phase of the cycle.
The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress
Strobe
Paper End
Printer
Selected Status
Error
EPP NAME
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a
"false" state.
TYPE
I/O
O
O
O
O
Table 9.2 - EPP Pin Descriptions
I
I
I
I
I
DATASHEET
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device
is ready for the next transfer.
This signal is active low. It is used to denote data read or
write operation.
This signal is active low. When driven active, the EPP device
is reset to its initial operational mode.
This signal is active low. It is used to denote address read or
write operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
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EPP DESCRIPTION
Revision 0.3 (10-26-04)