LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 136

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

21.2
21.3
21.4
Revision 0.3 (10-26-04)
Pin List of XNOR Chain
Pins 1 to 100 on the chip are inputs to the first XNOR chain, with the exception of the following:
1.
2.
3.
4.
5.
To put the chip in the first XNOR chain test mode, tie LAD0 (pin 10) and nLFRAME (pin 24) low. Then
toggle nPCI_RESET (pin 26) from a low to a high state. Once the chip is put into XNOR chain test mode,
LAD0 (pin 20) and nLFRAME (pin 24) become part of the chain.
To exit the first XNOR chain test mode tie LAD0 (pin 20) or nLFRAME (pin 24) high. Then toggle
nPCI_RESET (pin 26) from a low to a high state. A VCC POR will also cause the XNOR chain test mode
to be exited. To verify the test mode has been exited, observe the output at nIO_PME (pin 17). Toggling
any of the input pins in the chain should not cause its state to change.
Setup of XNOR Chain
Warning: Ensure power supply is off during setup.
1.
2.
3.
4.
Testing Procedure
1.
2.
3.
4.
5.
6.
7.
VCC (pins 13, 48, 53, 65 and 93) and VTR (pins 1, 18, 32 and 63).
VSS (pins 7, 19, 31, 39, 56, 60 and 76).
nIO_PME (pin 17) This is the chain output.
nPCI_RESET (pin 26).
XTAL1 (pin 61) and XTAL2 (pin 62)
Connect VSS (pins 7, 19, 31, 39, 56, 60 and 76) to ground.
Connect VCC (pins 13, 48, 53, 65 and 93) and VTR (pins 1, 18, 32 and 63) to VCC (3.3V).
Connect an oscilloscope or voltmeter to nIO_PME (pin 17).
All other pins should be tied to ground.
Turn power on.
With LAD0 (pin 20) and nLFRAME (pin 24), low, bring nPCI_RESET (pin 26) high. The chip is now in
XNOR chain test mode. At this point, all inputs to the first XNOR chain are low. The output, on
nIO_PME (pin 17), should also be low. Refer to INITIAL CONFIG on TRUTH TABLE 1.
Bring pin 100 high. The output on nIO_PME (pin 17) should go high. Refer to STEP ONE on TRUTH
TABLE 1.
In descending pin order, bring each input high. The output should switch states each time an input is
toggled. Continue until all inputs are high. The output on nIO_PME should now be low. Refer to END
CONFIG on TRUTH TABLE 1.
The current state of the chip is now represented by INITIAL CONFIG in TRUTH TABLE 2.
Each input should now be brought low, starting at pin one and continuing in ascending order. Continue
until all inputs are low. The output on nIO_PME should now be low. Refer to TRUTH TABLE 2.
To exit test mode, tie LAD0 (pin 20) OR nLFRAME (pin 24) high, and toggle nPCI_RESET from a low
to a high state.
DATASHEET
Page 136
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS – LPC47N237