LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 70

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

11.1.3 Stop Cycle Control
11.1.4 Latency
11.1.5 EOI/ISR Read Latency
11.1.6 AC/DC Specification Issue
Revision 0.3 (10-26-04)
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices Parallel Port and Serial Port have IRQ13
as a choice for their primary interrupt.
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating
a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the
SER_IRQ is low for two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ
Cycle’s sampled mode is the Quiet mode; and any SER_IRQ device may initiate a Start Frame in the
second clock or more after the rising edge of the Stop Frame’s pulse. If the Stop Frame’s low time is three
clocks then the next SER_IRQ Cycle’s sampled mode is the Continuos mode; and only the Host Controller
may initiate a Start Frame in the second clock or more after the rising edge of the Stop Frame’s pulse.
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host
supported IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84µS with a 25MHz PCI Bus or
2.88uS with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system, the latency for
IRQ/Data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses,
and approximately double for asynchronous buses.
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could
cause an EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a
system fault.
mitigated. The recommended solution is to delay EOIs and ISR Reads to the interrupt controller by the
same amount as the SER_IRQ Cycle latency in order to ensure that these events do not occur out of
order.
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus
clock. The SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI
spec. section 4, sustained tri-state.
SER_IRQ PERIOD
10
11
12
13
14
15
16
6
7
8
9
The host interrupt controller is responsible for ensuring that these latency issues are
DATASHEET
SIGNAL SAMPLED
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
Page 70
3.3v I/O Controller for Port Replicators and Docking Stations
# OF CLOCKS PAST START
17
20
23
26
29
32
35
38
41
44
47
SMSC DS – LPC47N237