LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 85

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
15.4.5 GPIO Change Status Register
15.5
SMSC DS – LPC47N237
There are four bits in the change status register – one for each data register. The change status register is
used indicate whether any of the data register bits (if GPIO is programmed as an input and unmasked) has
changed state since the last read of the data register. The change status register bit is cleared on the read
of the corresponding data register. See the “SMBus GPIO Register” section and “Operation of SMBus
Interrupt” section.
If any of the bits in this register is set to ‘1’, the nSMBINT pin will go active low. All bits in this register must
be cleared for the nSMBINT pin to be inactive high.
Operation of SMBus Interrupt
The operation of the GPIO pins, GPIO data register bits, change status register bits and nSMBINT pin is
summarized below.
Figure 15.2 shows two cases of GPIO transitions and the generation of the SMBus interrupt .
A change in the state of a GPIO pin is latched. A change in the state of the GPIO pin will never be
missed, even during a read of the data register.
If a GPIO pin changes more that once in between reads of the data register, the interrupt remains
active but the data bit will transition (as in case 2 of Figure 15.2 below).
If not masked, the change status register bit will be set and the interrupt pin will go active.
The change status register bit remains set and the interrupt stays active until the associated data
register is read.
The change status register bit and the interrupt is cleared in the start of the read of the associated
data register. Note: The nSMBINT pin is cleared when there are no bits set in the GPIO Change
Status Register.
Clearing the mask bit to ‘0’ will cause not an interrupt.
Writes to the GPIO data register while the GPIO pin is in output mode will not set the status change bit
and will not cause the interrupt to go active.
Writes to the GPIO data register while the GPIO pin is in input mode will not set the status change bit
and will not cause the interrupt to go active. The data that is written will be stored in the GPIO output
buffer, and when the GPIO is switched from input to output, what is in the output buffer is reflected on
the pin.
Glitch filtering is implemented as follows: Min 15ns, Max 100ns (40ns typical)
DATASHEET
Page 85
Revision 0.3 (10-26-04)