UPD17073 NEC, UPD17073 Datasheet - Page 128

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

128
Direct division (MF)
Division mode
Pulse swallow
Pulse swallow
(VHF)
reset
(HF)
At
PLL mode select
register
Power-ON
Clock stop
CE
Name
VCOH
VCOL
VCOL
Figure 15-3. Configuration of PLL Mode Select Register
Pin
Table 15-1. Input Pins and Division Modes
b
0
0
3
Flag symbol
Input frequency
b
0
0
2
40 - 230
5 - 130
0.3 - 8
Retained
(MHz)
M
b
D
P
L
L
1
0
1
1
0
0
0
1
M
D
b
P
L
L
0
0
1
0
1
0
0
0
(BANK1)
Address
PLL disabled
Direct division (VCOL pin MF mode)
Pulse swallow (VCOH pin VHF mode, 1/2 division)
Pulse swallow (VCOL pin HF mode)
Fixed to "0"
65H
Input amplitude
Sets division mode of PLL frequency synthesizer
(V
0.2
0.3
0.2
p-p
Read/
Write
R/W
)
1024 to 2
1024 to 2
Division value
16 to 2
12
17
17
– 1
– 1
– 1
Division value set
0400H – 1FFFFH
0400H – 1FFFFH
010xH - FFFxH
(x: don’t care)
to data buffer
PD17072,17073