UPD17073 NEC, UPD17073 Datasheet - Page 186
UPD17073
Manufacturer Part Number
UPD17073
Description
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
Manufacturer
NEC
Datasheet
1.UPD17073.pdf
(226 pages)
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19.6.4 Inputting signal to CE pin
malfunctioning due to noise.
19.6.5 Configuration and functions of CE pin status detection register
186
Remark –: Determined by status of pin
The CE pin does not accept a low- or high-level signal less than 200 s in order to protect the system from
The level of the signal input to the CE pin can be detected by using the CE flag of the CE pin status detection.
Figure 19-5 shows the relations between the input signal and CE flag.
The CE pin status detection register detects the level of the signal input to the CE pin.
The configuration and functions of this register are illustrated below.
The CE flag does not change even if a low or high level signal less than 200 s is input.
CE flag
CE pin
reset
At
detection register
H
CE pin status
L
1
0
Power-ON
Clock stop
CE
Figure 19-5. Relations between Signal Input to CE Pin and CE Flag
Name
Figure 19-6. Configuration of CE Pin Status Detection Register
less than
PLL enabled
STOP s invalid (NOP)
200 s
b
0
0
3
Flag symbol
b
0
0
2
b
0
0
1
200 s
b
0
1
_
_
_
C
E
0
(BANK1)
Low level
High level
Fixed to "0"
Address
52H
less than
200 s
PLL disabled
STOP s valid
Read/
Write
Detects status of CE pin
R
200 s
PLL disabled
STOP s invalid (NOP)
CE reset is effected in
synchronization with
next setting of
basic timer 0 carry FF
CE reset
PD17072,17073
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