UPD17073 NEC, UPD17073 Datasheet - Page 181
UPD17073
Manufacturer Part Number
UPD17073
Description
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
Manufacturer
NEC
Datasheet
1.UPD17073.pdf
(226 pages)
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19.4 Device Operations in Halt and Clock Stop Statuses
stopped.
initialized) in the halt status, but is initialized to a specified value in the clock stop status (when the “STOP s” instruction
is executed).
operation status is determined by the initialized value of the peripheral control register in the clock stop status.
Hardware Functions of Peripheral Control Register.
, and serial communication is started in
and the halt status is released when the interrupt by the serial interface is accepted.
peripheral control registers set in
and all the pins of the port 0B are set in the general-purpose input port mode.
Example When P1C0/SO0 pin of port 1C is specified as output port pin, and P0B3/SI/SO1 pin and P0B2/SCK
Table 19-1 shows the operations of the CPU and peripheral hardware in the halt and clock stop statuses.
In the halt status, all the peripheral hardware continue the normal operation, except that instruction execution is
In the clock stop status, all peripheral hardware stop.
The peripheral control register that controls the operating status of the peripheral hardware operates normally (not
Each peripheral hardware continues the operation set in the peripheral control register in the halt status, and its
For the value to which the peripheral control register is to be initialized, refer to chapter Table 8-1. Peripheral
Here is an example:
In the above example, the P0B3, P0B2 pins output high level in
When the “HALT” instruction is executed in
If the “STOP” instruction in
pins are used for serial interface
HLTINT
XTAL
INITFLG
;<1>
SET3
;<2>
BANK1
CLR1
INITFLG
INITFLG
SET1
EI
;<3>
SET1
;<4>
HALT
;<5>
STOP
DAT
DAT
P0BBIO3,P0BBIO2
P0B3, P0B2
IRQSIO
SIOCK1, SIOCK0
SIOSEL, NOT SIOHIZ
IPSIO
SIOTS
HLTINT
XTAL
<5>
<1>
is executed instead of the “HALT” instruction in
,
1000B
0000B
<2>
<3>
, and
.
<4>
<3>
, the halt status is set, but the serial communication continues,
are initialized. Consequently, serial communication is stopped,
<1>
, the condition of serial interface is set in
<4>
PD17072,17073
, the contents of all the
<2>
181
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