UPD17073 NEC, UPD17073 Datasheet - Page 74

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

11.6.2 Timing to accept interrupt
the interrupt enable flag is set to “1” last.
enable flag have been set.
satisfied that sets the last flag or flip-flop to “1”, the interrupt is accepted during the second instruction cycle of the
“MOVT DBF, @AR” instruction or when the skipped instruction (“NOP”) has been executed.
the interrupt enable flags are set. However, the hardware priority can be changed by manipulating the interrupt enable
flag through program.
specified, and the contents of the program counter are saved after an interrupt has been accepted, and lasts for 53.3
74
s, (normal operation) or one instruction execution time.
Figure 11-8 is a timing chart illustrating how interrupts are accepted.
(1)
(a)
In either case, the interrupt is accepted after all the interrupt request flag, interrupt enable flip-flop, and interrupt
If it is during the first instruction cycle of the “MOVT DBF, @AR” instruction or an instruction with the skip condition
The interrupt enable flip-flop is set in the instruction cycle next to the one in which the “EI” instruction is executed.
(2) in Figure 11-8 shows the timing chart where two or more interrupts are used.
When using two or more interrupts, the interrupt given the highest hardware priority at that time is accepted if all
“Interrupt cycle” in Figure 11-8 is a special cycle in which the interrupt request flag is clear, a vector address is
For details, refer to 11.7 Operations after Accepting Interrupt.
in this figure illustrate how one type of interrupt is accepted.
in (1) indicates the case where the interrupt request flag is set to “1” last, while (b) shows the case where
PD17072,17073