UPD17073 NEC, UPD17073 Datasheet - Page 191

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

20.3.2 CE reset when clock stop mode (STOP s instruction) is used
s” instruction has been executed.
by the basic timer 0 carry, is set.
mode is released and oscillation is started.
pin has risen, the oscillation stabilization status lasts (for 125 ms or longer). If the basic timer 0 carry FF setting pulse
rises after that, the halt status is released, and program execution is started from address 0.
20.3.3 Notes on CE reset
be noted.
(1) Time for executing timer processing such as watch
(2) Processing of data or flag used in program
Figure 22-3 shows the operation.
When the clock stop mode is used, the IRES, RES, and RESET signals are output at the point where the “STOP
While the CE pin is low, output of the IRES signal continues; therefore, the forced halt status, which is released
However, the device stops operation because the clock is stopped. When the CE pin goes high, the clock stop
At this time, the halt status that is released by the basic timer 0 carry FF is set by the IRES signal. After the CE
Because CE reset is effected regardless of the instruction under execution, the following points (1) and (2) must
Reset
signals
Basic timer 0 carry
FF setting pulse
To create a watch program by using the basic timer 0 or basic timer 1, the processing of the program must
be completed within specific time.
For details, refer to 12.2.5 Notes on using basic timer 0 and 12.3.4 Notes on using basic timer 1.
Exercise care in rewriting data or flags that cannot be processed with one instruction and whose contents must
not be changed even if CE reset is effected, such as security code.
Here is an example:
V
CE
X
IRES
RES
RESET
DD
OUT
Figure 20-3. CE Reset Operation When Clock Stop Mode Is Used
3 V
0 V
H
L
H
L
H
L
H
L
H
L
H
L
Normal operation
STOP 0000B instruction Clock stop released.
Clock stop status
Oscillation starts.
Halt status
or more
125 ms
CE reset
Program starts from address 0.
PD17072,17073
191