UPD17073 NEC, UPD17073 Datasheet - Page 141

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

15.6.2 Pulse swallow mode (HF)
(1) Selecting division mode
(2) Pin to be used
(3) Setting reference frequency f
(4) Calculating division value N
(5) Example of PLL data setting
Then set the PLL data register, PLL mode select register, and PLL reference frequency select register as follows:
Select the pulse swallow mode by the PLL mode select register.
The VCOL pin is enabled when the pulse swallow mode is selected.
Set the reference frequency by using the PLL reference frequency select register.
Calculate as follows:
where,
Suppose that broadcasting in the following SW band is to be received:
The division ratio N is:
N =
Receive frequency
Reference frequency
Intermediate frequency
N =
0
f
f
f
0
VCOL
f
VCOL
r
VCOL
f
r
f
r
0
1
: input frequency of VCOL pin
: reference frequency
0
=
1
25500 + 450
0
1
PLL data register
5
4
:
:
:
0
r
25.50 MHz (SW band)
0
+450 kHz
0
5 kHz
= 5190 (decimal)
= 1446H (hexadecimal)
1
4
0
0
0
1
6
1
0
0
PLL mode
select
register
0
HF
1
1
PD17072,17073
PLL reference
frequency
select register
0
5 kHz
0
1
0
141