UPD17073 NEC, UPD17073 Datasheet - Page 51

• Manufacturer Part Number: UPD17073
• Description: 4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE FOR DIGITAL TUNING SYSTEM
• Manufacturer: NEC

Peripheral
hardware
PLL
frequency register
synthesizer
Note
Remark U: Undefined, R: Previous status is retained.
PLL mode select
PLL reference
frequency select
register
PLL data register
PLL data set
register
PLL unlock FF
register
For the details of the set value, refer to Figure 15-4 Configuration of PLL Data Register.
Name
Table 8-1. Peripheral Hardware Control Functions of Peripheral Control Registers (2/4)
Control register
(BANK1) R/W
(BANK1) R/W
(BANK1) R/W
(BANK1)
(BANK1)
(BANK1)
(BANK1)
(BANK1) W
(BANK1) R&
Address
6CH
6DH
65H
66H
67H
68H
69H
6AH
6BH
Read/ b
Reset 0
Write b
– – – – – – – – -
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – -
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – -
– – – – – – – – -
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – –
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – -
– – – – – – – – -
– – – – – – – – -
– – – – – – – – -
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
– – – – – – – – -
– – – – – – – – -
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
b
b
0
0
PLLMD1
PLLMD0
0
PLLRFCK2 Sets reference frequency of PLL
PLLRFCK1
PLLRFCK0
PLLR17
PLLR16
PLLR15
PLLR14
PLLR13
PLLR12
PLLR11
PLLR10
PLLR9
PLLR8
PLLR7
PLLR6
PLLR5
PLLR4
PLLR3
PLLR2
PLLR1
0
0
0
0
0
0
PLLPUT
0
0
PLLUL
3
2
1
0
Symbol
Fixed to 0
Sets division mode of PLL
Fixed to 0
Sets division ratio of PLL
Fixed to 0
Fixed to 0
Data transfer to programmable counter
Fixed to 0
Detects status of unlock FF
Functional outline
Peripheral hardware control function
0
0
0:1 kHz 1:3 kHz 2:5 kHz
3:6.25 kHz 4:12.5 kHz
5:25 kHz 6, 7: PLL disable
• In direct division mode
• In pulse swallow mode
Does not transfer Transfers
Locked status
Disable
PLLR6-PLLR17: Valid data
PLLR1-PLLR5: don’t care
0-15 (000H-00FH):
16-2
PLLR1-PLLR17: Valid data
0-1023 (0000H-03FFH):
1024-2
Setting prohibited
Can be set
Setting prohibited
Can be set
12
0
– 1 (010H-FFFH):
17
0
1
– 1 (0400H-1FFFFH):
Set value
MF
Note
Note
PD17072,17073
1
0
Unlocked status
VHF
1
1
1
HF
Power- Clock CE
ON stop
U
U
0
0
0
At reset
0
R
R
0
0
51
R
R
R
R
0