S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 1001
S9S12G128F0VLL
Manufacturer Part Number
S9S12G128F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
86
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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28.3.2.9.1
The general guideline is that P-Flash protection can only be added and not removed.
all valid transitions between P-Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario.
See the FPHS and FPLS bit descriptions for additional restrictions.
28.3.2.10 EEPROM Protection Register (EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
1
The (unreserved) bits of the EEPROT register are writable with the restriction that protection can be added
but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1
(protection disabled) to 0 (protection enabled). If the DPOPEN bit is set, the state of the DPS bits is
irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents
of the EEPROM protection byte in the Flash configuration field at global address 0x3_FF0D located in
Freescale Semiconductor
Loaded from IFR Flash configuration field, during reset sequence.
Offset Module Base + 0x0009
Reset
W
R
DPOPEN
F
7
1
P-Flash Protection Restrictions
1
Protection
Allowed transitions marked with X, see
Scenario
From
0
1
2
3
4
5
6
7
F
6
Figure 28-15. EEPROM Protection Register (EEPROT)
Table 28-21. P-Flash Protection Scenario Transitions
1
X
X
0
MC9S12G Family Reference Manual, Rev.1.23
F
5
1
X
X
X
X
1
X
X
X
X
2
To Protection Scenario
F
4
1
Figure 28-14
X
X
X
X
X
X
X
X
3
DPS[6:0]
X
X
X
X
F
4
for a definition of the scenarios.
3
1
1
5
X
X
96 KByte Flash Module (S12FTMRG96K1V1)
F
2
1
X
X
6
Table 28-21
X
7
F
1
1
specifies
F
0
1
1003
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