S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 176

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Port Integration Module (S12GPIMV1)
178
PP3-PP2
PP1
PP0
• Except 20 TSSOP: The PWM channels 3 and 2 signal are mapped to these pins when used with the
• Except 20 TSSOP: The ADC ETRIG 3 and 2 signal are mapped to these pins when used with the ADC
• Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• Except 20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function.
• Except 100 LQFP and 20 TSSOP: The ECLKX2 signal is mapped to this pin when used with the
• Except 20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function.
• Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• Except 20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function.
• Except 100 LQFP and 20 TSSOP: The API_EXTCLK signal is mapped to this pin when used with the
• Except 20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function.
• Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
PWM function. The enabled PWM channel forces the I/O state to be an output.
function. The enabled external trigger function has no effect on the I/O state. Refer to
“ADC External Triggers
Except 20 TSSOP: PWM > GPO
The enabled PWM channel forces the I/O state to be an output.
external clock function. The enabled ECLKX2 forces the I/O state to an output.
The enabled external trigger function has no effect on the I/O state. Refer to
External Triggers
Except 100 LQFP and 20 TSSOP: PWM1 > ECLKX2 > GPO
100 LQFP: PWM1 > GPO
The enabled PWM channel forces the I/O state to be an output.
external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O
state is forced to output.
The enabled external trigger function has no effect on the I/O state. Refer to
External Triggers
Except 100 LQFP and 20 TSSOP: PWM0 > API_EXTCLK > GPO
100 LQFP: PWM0 > GPO
Table 2-14. Port
MC9S12G Family Reference Manual,
ETRIG3-0”.
ETRIG3-0”.
ETRIG3-0”.
P
Pins PP7-0 (continued)
Rev.1.23
Section 2.6.4, “ADC
Section 2.6.4, “ADC
Freescale Semiconductor
Section 2.6.4,