S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 606
S9S12G128F0VLL
Manufacturer Part Number
S9S12G128F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
86
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
1
Module Base + 0x001C to Module Base + 0x001F
Module Base + 0x0014 to Module Base + 0x0017
Freescale’s Scalable Controller Area Network (S12MSCANV3)
608
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AM[7:0]
AM[7:0]
Field
Field
7-0
7-0
Reset
Reset
Figure 18-23. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Figure 18-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
W
W
R
R
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
AM7
AM7
0
7
0
7
Table 18-24. CANIDMR0–CANIDMR3 Register Field Descriptions
Table 18-25. CANIDMR4–CANIDMR7 Register Field Descriptions
AM6
AM6
0
6
0
6
MC9S12G Family Reference Manual,
AM5
AM5
0
5
0
5
AM4
AM4
0
Description
Description
4
0
4
AM3
AM3
0
3
0
3
Rev.1.23
AM2
AM2
0
2
0
2
Freescale Semiconductor
Access: User read/write
Access: User read/write
AM1
AM1
0
1
0
1
AM0
AM0
0
0
0
0
1
1
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