S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 325

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S9S12G128F0VLL

Manufacturer Part Number
S9S12G128F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G128F0VLL

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
86
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V

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register bytes (three address bus compare registers and a control register). Comparator C consists of four
register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register.
Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be
written. The control register for comparator B differs from those of comparators A and C.
8.3.2.8.1
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Freescale Semiconductor
Address: 0x0028
Address: 0x0028
Address: 0x0028
0x002C
0x002D
0x002A
0x002B
0x002E
0x002F
0x0028
0x0029
Reset
Reset
Reset
W
W
W
R
R
R
SZE
SZE
0
0
0
0
7
7
7
Debug Comparator Control Register (DBGXCTL)
Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A)
Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B)
Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C)
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
SZ
SZ
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
6
CONTROL
MC9S12G Family Reference Manual, Rev.1.23
Table 8-21. Comparator Register Layout
TAG
TAG
TAG
0
0
0
5
5
5
BRK
BRK
BRK
0
0
0
4
4
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
RW
RW
RW
0
0
0
3
3
3
RWE
RWE
RWE
0
0
0
2
2
2
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
S12S Debug Module (S12SDBGV2)
Comparator A only
Comparator A only
Comparator A only
Comparator A only
NDB
0
0
0
0
0
1
1
1
COMPE
COMPE
COMPE
0
0
0
0
0
0
327

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