S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 204

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S9S12G128F0VLL

Manufacturer Part Number
S9S12G128F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G128F0VLL

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
86
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V

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1
1
Port Integration Module (S12GPIMV1)
2.4.3.3
206
Address 0x0002 (G1)
Address 0x0002 (G2, G3)
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Read: Anytime
Write: Anytime
DDRA
Field
Field
Reset
Reset
7-0
7-0
PB
W
W
R
R
Port B general-purpose input/output data—Data Register
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
DDRA7
Port A Data Direction Register (DDRA)
0
0
0
7
7
DDRA6
0
0
0
6
6
Figure 2-4. Port A Data Direction Register (DDRA)
Table 2-23. PORTB Register Field Descriptions
Table 2-24. DDRA Register Field Descriptions
MC9S12G Family Reference Manual,
DDRA5
0
0
0
5
5
DDRA4
0
0
0
4
4
Description
Description
DDRA3
3
0
3
0
0
Rev.1.23
DDRA2
0
0
0
2
2
Freescale Semiconductor
DDRA1
Access: User read/write
Access: User read only
0
0
0
1
1
DDRA0
0
0
0
0
0
1

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