S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 222
S9S12G128F0VLL
Manufacturer Part Number
S9S12G128F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G128F0VLL
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
86
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G128F0VLLR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
1
Port Integration Module (S12GPIMV1)
2.4.3.28
2.4.3.29
224
Address 0x0251 (G1, G2)
Address 0x0251 (G3)
Address 0x0252 (G1, G2)
Address 0x0252 (G3)
Read: Anytime
Write:Never
Read: Anytime
Write: Anytime
Field
PTIM
Reset
Reset
Reset
Reset
3-0
W
W
W
W
R
R
R
R
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Port M Input Register (PTIM)
0
0
0
0
Port M Data Direction Register (DDRM)
0
0
0
0
7
7
7
7
0
0
0
0
0
0
0
0
6
6
6
6
Figure 2-30. Port M Data Direction Register (DDRM)
Table 2-53. PTIM Register Field Descriptions
Figure 2-29. Port M Input Register (PTIM)
MC9S12G Family Reference Manual,
0
0
0
0
0
0
0
0
5
5
5
5
0
0
0
0
0
0
0
0
4
4
4
4
Description
DDRM3
PTIM3
3
0
3
0
0
3
0
3
0
0
Rev.1.23
DDRM2
PTIM2
0
0
0
0
0
0
2
2
2
2
DDRM1
Freescale Semiconductor
DDRM1
PTIM1
PTIM1
Access: User read/write
Access: User read/write
Access: User read only
Access: User read only
0
0
0
0
1
1
1
1
DDRM0
DDRM0
PTIM0
PTIM0
0
0
0
0
0
0
0
0
1
1
1
1
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