S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 660

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Pulse-Width Modulator (S12PWM8B8CV2)
Shown in
19.4.2.7
The scalable PWM timer also has the option of generating up to 8-channels of 8-bits or 4-channels of
16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of
two 8-bit channels.
The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and
5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and
channels 0 and 1 are concatenated with the CON01 bit.
When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double
byte channel, as shown in
registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated,
channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are
concatenated, channel 0 registers become the high order bytes of the double byte channel.
When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel
clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when
channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when
channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order
8-bit channel as also shown in
PPOLx bit of the corresponding low order 8-bit channel as well.
662
E = 100 ns
Clock Source = E, where E = 10 MHz (100 ns period)
Figure 19-20
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
PWMx Frequency = 10 MHz/8 = 1.25 MHz
PWMx Period = 800 ns
PWMx Duty Cycle = 3/4 *100% = 75%
PWM 16-Bit Functions
Change these bits only when both corresponding channels are disabled.
Figure 19-20. PWM Center Aligned Output Example Waveform
is the output waveform generated.
Figure
Figure
MC9S12G Family Reference Manual,
19-21. Similarly, when channels 4 and 5 are concatenated, channel 4
19-21. The polarity of the resulting PWM output is controlled by the
DUTY CYCLE = 75%
PERIOD = 800 ns
NOTE
Rev.1.23
Freescale Semiconductor
E = 100 ns