S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 172

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Port Integration Module (S12GPIMV1)
174
PT4
PT3-PT2
PT1
PT0
• 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function.
• Signal priority:
• Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the
• Signal priority:
• Except 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If
• The TIM channel 1 signal is mapped to this pin when used with the timer function. The TIM forces the
• Signal priority:
• Except 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt
• The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the
• Signal priority:
The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare.
48/64/100 LQFP: IOC4 > GPO
timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled
output compare.
Except 20 TSSOP: IOC3-2 > GPO
enabled (IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input.
I/O state to be an output for a timer port associated with an enabled output compare.
100 LQFP: IOC1 > GPO
Others: IRQ > IOC1 > GPO
function.The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The
I/O state of the pin is forced to input level upon the first clearing of the X bit and held in this state even
if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference
Manual) is not available.
I/O state to be an output for a timer port associated with an enabled output compare.
100 LQFP: IOC0 > GPO
Others: XIRQ > IOC0 > GPO
Table 2-11. Port
MC9S12G Family Reference Manual,
T
Pins PT7-0 (continued)
Rev.1.23
Freescale Semiconductor