S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 738

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Timer Module (TIM16B6CV3)
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
22.3.2.6
Read: Anytime
Write: Anytime
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
740
Module Base + 0x0008
Module Base + 0x0009
TOV[5:0]
Reset
Reset
Field
Field
OMx
OLx
5:0
5:0
5:0
W
W
R
R
RESERVED RESERVED RESERVED RESERVED
OM3
Toggle On Overflow Bits — TOVx toggles output compare pin on overflow. This feature only takes effect when
in output compare mode. When set, it takes precedence over forced output compare
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
Output Mode — These six pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: For an output line to be driven by an OCx the OCPDx must be cleared.
Output Level — These sixpairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: For an output line to be driven by an OCx the OCPDx must be cleared.
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
0
0
7
7
OL3
0
0
6
6
Figure 22-10. Timer Control Register 1 (TCTL1)
Figure 22-11. Timer Control Register 2 (TCTL2)
Table 22-6. TCTL1/TCTL2 Field Descriptions
MC9S12G Family Reference Manual,
Table 22-5. TTOV Field Descriptions
OM2
0
0
5
5
OL2
0
0
4
4
Description
Description
OM5
OM1
0
0
3
3
Rev.1.23
OL5
OL1
0
0
2
2
Freescale Semiconductor
OM4
OM0
0
0
1
1
OL4
OL0
0
0
0
0