S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 786

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S9S12G128F0VLL

Manufacturer Part Number
S9S12G128F0VLL
Description
16-bit Microcontrollers - MCU 16BIT 128K FLASH
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12G128F0VLL

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
1 MHz
Program Memory Size
128 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-100
Mounting Style
SMD/SMT
A/d Bit Size
10 bit, 12 bit
A/d Channels Available
12
Interface Type
SPI
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
86
Number Of Timers
8
Program Memory Type
Flash
Supply Voltage - Max
5.5 V
Supply Voltage - Min
3.13 V

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16 KByte Flash Module (S12FTMRG16K1V1)
24.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
788
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
0x0011
0x0012
0x0013
FRSV5
FRSV6
FRSV7
Field
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Flash Clock Divider Register (FCLKDIV)
0
7
W
W
W
R
R
R
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
7
0
0
0
FDIVLCK
Figure 24-4. FTMRG16K1 Register Summary (continued)
= Unimplemented or Reserved
0
6
Figure 24-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
6
0
0
0
MC9S12G Family Reference Manual,
Table 24-7. FCLKDIV Field Descriptions
0
5
5
0
0
0
CAUTION
0
4
Description
4
0
0
0
0
3
FDIV[5:0]
3
0
0
0
Rev.1.23
0
2
2
0
0
0
Freescale Semiconductor
0
1
1
0
0
0
0
0
0
0
0
0

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