S9S12G128F0VLL Freescale Semiconductor, S9S12G128F0VLL Datasheet - Page 765

• Manufacturer Part Number: S9S12G128F0VLL
• Description: 16-bit Microcontrollers - MCU 16BIT 128K FLASH
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G128F0VLL

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 86
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Module Base + 0x0010 = TC0H
Module Base + 0x0011 = TC0L
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
23.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–
1
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during
input capture. All timer input capture/output compare registers are reset to 0x0000.
Freescale Semiconductor
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Field
TOF
7
Reset
Reset
W
W
R
R
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one
(See also TCRE control bit explanation.)
0x0012 = TC1H
0x0014=TC2H
0x0016=TC3H
0x0013 = TC1L
0x0015 =TC2L
0x0017=TC3L
7(TCxH and TCxL)
Read/Write access in byte mode for high byte should take place before low
byte otherwise it will give a different result.
Figure 23-22. Timer Input Capture/Output Compare Register x High (TCxH)
Figure 23-23. Timer Input Capture/Output Compare Register x Low (TCxL)
Bit 15
Bit 7
15
0
0
7
Bit 14
Bit 6
14
0
0
6
MC9S12G Family Reference Manual, Rev.1.23
Table 23-17. TRLG2 Field Descriptions
0x0018=TC4H
0x001A=TC5H
0x001C=TC6H
0x001E=TC7H
0x0019 =TC4L
0x001B=TC5L
0x001D=TC6L
0x001F=TC7L
Bit 13
Bit 5
13
0
0
5
NOTE
Bit 12
Bit 4
12
0
0
4
Description
Bit 11
Bit 3
11
0
0
3
Bit 10
Bit 2
10
0
0
2
Timer Module (TIM16B8CV3)
Bit 9
Bit 1
0
0
9
1
Bit 8
Bit 0
0
0
0
0
767