MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 1058
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MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Universal Serial Bus Interface
States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB_DR and are
communicated to the DCD using the following status bits:
It is the responsibility of the DCD to maintain a state variable to differentiate between the DefaultFS/HS
state and the Address/Configured states. Change of state from Default to Address and the Configured
states is part of the enumeration process described in the device framework section of the USB 2.0
Specification.
16-130
Resets the Device
When the Host
Returns to the
Default State
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Software Only State
Interruption
Power
Deconfigured
Table 16-83. Device Controller State Information Bits
DCSuspend (SLI)
USB Reset Received (URI)
Port Change Detect (PCI)
High-Speed Port
Device
Active State
Configured
Figure 16-63. USB 2.0 Device States
Powered
Address
Default
FS/HS
FS/HS
FS/HS
Attach
Address Assigned
Bits
Configured
Device
Reset
Set Run/Stop Bit
to Run Mode
Bus Inactive
Bus Inactive
Bus Inactive
Bus Activity
Bus Activity
Bus Activity
PORTSC
Register
USBSTS
USBSTS
USBSTS
Inactive State
Suspend
Suspend
Suspend
FS/HS
FS/HS
FS/HS
Freescale Semiconductor
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