MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 185

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

4.3.2.2.5
The TSEC1 mode reset configuration word field, shown in
eTSEC1 controller (enhanced three-speed Ethernet controller interface).
Freescale Semiconductor
Reset Configuration
Word High Register
(RCWHR) Bits
16–18
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
eTSEC1 Mode
The reset value of the system I/O configuration register high (SICRH)
depends on the reset configuration word high TSEC1M field setting. This is
used to avoid contention in systems not using the RTBI modes. In non-TBI
modes, device signals which have additional functions are set to be in a
non-TSEC function, thus not driven during and after reset. The function of
these signals can be changed by writing to this register during system
initialization. See
(SICRH).”
Field Name
TSEC1M
Section 5.3.2.6, “System I/O Configuration Register High
Table 4-16. eTSEC1 Mode Configuration
(Binary)
Value
000
001
010
011
100
101
110
111
The eTSEC1 controller operates in the MII protocol, using only four
transmit data signals and four receive data signals.
The eTSEC1 controller operates in the RMII protocol, using only two
transmit data signals and two receive data signals.
Reserved
The eTSEC1 controller operates in the RGMII protocol, using four
transmit data signals and four receive data signals.
Reserved
The eTSEC1 controller operates in the RTBI protocol, using only four
transmit data signals and four receive data signals.
The eTSEC1 controller operates in the SGMII protocol, using the
on-chip PHY.
Reserved
NOTE
Table
4-16, selects the protocol used by the
Meaning
Reset, Clocking, and Initialization
4-19