MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 493
MPC8313EZQADDC
Manufacturer Part Number
MPC8313EZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB W/ENC
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313EZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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It is very important to ensure that the value of LBCR[BMT] is not set too low; otherwise spurious bus
time-outs may occur during normal operation—resulting in incomplete data transfers. Accordingly, the
time-out value represented by the LBCR[BMT], LBCR[BMTPS] pair must not be set below 40 bus cycles
for time-out under any circumstances.
10.4.2
The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM
devices, and external peripherals. The GPCM contains two basic configuration register groups—BR
OR
Figure 10-32
mode. Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output
enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
Figure 10-33
can configure OR
cycle are taken from OR
fields.
Freescale Semiconductor
n
.
General-Purpose Chip-Select Machine (GPCM)
shows a simple connection between an 8-bit port size SRAM device and the eLBC in GPCM
shows LCS as defined by the setup time required between the address lines and CE. The user
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
eLBC in GPCM
n
[ACS] to specify LCS to meet this requirement. Generally, the attributes for the memory
Mode
Figure 10-32. Enhanced Local Bus to GPCM Device Interface
n
. These attributes include the CSNT, ACS, XACS, SCY, TRLX, EHTR and SETA
LAD[0:7]
LA[6:25]
LWE0
LCS n
LOE
CE
OE
WE
Data[7:0]
A[19:0]
Memory/Peripheral
Enhanced Local Bus Controller
n
10-45
and
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