MPC8313EZQADDC Freescale Semiconductor, MPC8313EZQADDC Datasheet - Page 780

• Manufacturer Part Number: MPC8313EZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB W/ENC
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313EZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Three-Speed Ethernet Controllers
15.5.3.3.10 Receive Data Buffer Pointer High Register (RBDBPH)
The RBDBPH register is written by the user with the most significant address bits common to all RxBD
buffer addresses, RxBD[Data Buffer Pointer]. As a consequence, Rx buffers must be placed in a 4 Gbyte
segment of memory whose base address is prefixed by the bits in RBDBPH. The RxBD ring itself can
reside in a different memory region (based at RBASEH).
RBDBPH register.
Table 15-36
15.5.3.3.11 Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7)
RBPTR0–RBPTR7 each contains the low-order 32 bits of the next receive buffer descriptor address for
their respective RxBD ring.
value of their ring’s associated RBASE when the RBASE register is written by software. Software must
not write RBPTRn while eTSEC is actively receiving frames. However, RBPTRn can be modified when
the receiver is disabled or when no Rx buffer is in use (after a GRACEFUL STOP RECEIVE command is
issued and the frame completes its reception) in order to change the next RxBD eTSEC receives.
15-62
28–31
0–27
Bits
Offset eTSEC1:0x2_4384+8× n ; eTSEC2:0x2_5384+8× n
Offset eTSEC1:0x2_4380; eTSEC2:0x2_5380
Reset
Reset
W
W
R
R
RBDBPH Most significant bits common to all data buffer addresses contained in RxBDs. The user must initialize
0
0
Name
—
describes the fields of the RBDBPH register.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
RBDBPH before enabling the eTSEC receive function.
Figure 15-33. RBPTR0–RBPTR7 Register Definition
Figure 15-33
Figure 15-32. RBDBPH Register Definition
Table 15-36. RBDBPH Field Descriptions
describes the RBPTR registers. These registers takes on the
RBPTR n
—
All zeros
All zeros
Description
Figure 15-32
describes the definition for the
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27 28
28 29
RBDBPH
—
31
31